ARM: 9263/1: use .arch directives instead of assembler command line flags
Similar to commita6c30873ee
("ARM: 8989/1: use .fpu assembler directives instead of assembler arguments"). GCC and GNU binutils support setting the "sub arch" via -march=, -Wa,-march, target function attribute, and .arch assembler directive. Clang was missing support for -Wa,-march=, but this was implemented in clang-13. The behavior of both GCC and Clang is to prefer -Wa,-march= over -march= for assembler and assembler-with-cpp sources, but Clang will warn about the -march= being unused. clang: warning: argument unused during compilation: '-march=armv6k' [-Wunused-command-line-argument] Since most assembler is non-conditionally assembled with one sub arch (modulo arch/arm/delay-loop.S which conditionally is assembled as armv4 based on CONFIG_ARCH_RPC, and arch/arm/mach-at91/pm-suspend.S which is conditionally assembled as armv7-a based on CONFIG_CPU_V7), prefer the .arch assembler directive. Add a few more instances found in compile testing as found by Arnd and Nathan. Link:1d51c699b9
Link: https://bugs.llvm.org/show_bug.cgi?id=48894 Link: https://github.com/ClangBuiltLinux/linux/issues/1195 Link: https://github.com/ClangBuiltLinux/linux/issues/1315 Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
This commit is contained in:
parent
5aa4860eb5
commit
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@ -164,4 +164,3 @@ $(obj)/piggy_data: $(obj)/../Image FORCE
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$(obj)/piggy.o: $(obj)/piggy_data
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CFLAGS_font.o := -Dstatic=
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AFLAGS_hyp-stub.o := -Wa,-march=armv7-a
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@ -13,7 +13,5 @@ obj-$(CONFIG_SHARP_SCOOP) += scoop.o
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obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
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obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
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CFLAGS_REMOVE_mcpm_entry.o = -pg
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AFLAGS_mcpm_head.o := -march=armv7-a
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AFLAGS_vlock.o := -march=armv7-a
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obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o
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obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o
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@ -15,6 +15,8 @@
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#include "vlock.h"
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.arch armv7-a
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.if MCPM_SYNC_CLUSTER_CPUS
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.error "cpus must be the first member of struct mcpm_sync_struct"
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.endif
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@ -12,6 +12,8 @@
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#include <linux/linkage.h>
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#include "vlock.h"
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.arch armv7-a
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/* Select different code if voting flags can fit in a single word. */
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#if VLOCK_VOTING_SIZE > 4
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#define FEW(x...)
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@ -71,7 +71,6 @@ obj-$(CONFIG_HAVE_TCM) += tcm.o
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obj-$(CONFIG_OF) += devtree.o
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obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
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obj-$(CONFIG_SWP_EMULATE) += swp_emulate.o
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CFLAGS_swp_emulate.o := -Wa,-march=armv7-a
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obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
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obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
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@ -100,7 +99,6 @@ CFLAGS_head-inflate-data.o := $(call cc-option,-Wframe-larger-than=10240)
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obj-$(CONFIG_XIP_DEFLATED_DATA) += head-inflate-data.o
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obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o
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AFLAGS_hyp-stub.o :=-Wa,-march=armv7-a
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ifeq ($(CONFIG_ARM_PSCI),y)
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obj-$(CONFIG_SMP) += psci_smp.o
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endif
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@ -9,6 +9,8 @@
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#include <asm/assembler.h>
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#include <asm/virt.h>
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.arch armv7-a
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#ifndef ZIMAGE
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/*
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* For the kernel proper, we need to find out the CPU boot mode long after
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@ -34,6 +34,7 @@
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*/
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#define __user_swpX_asm(data, addr, res, temp, B) \
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__asm__ __volatile__( \
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".arch armv7-a\n" \
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"0: ldrex"B" %2, [%3]\n" \
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"1: strex"B" %0, %1, [%3]\n" \
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" cmp %0, #0\n" \
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@ -36,10 +36,6 @@ else
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lib-y += io-readsw-armv4.o io-writesw-armv4.o
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endif
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ifeq ($(CONFIG_ARCH_RPC),y)
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AFLAGS_delay-loop.o += -march=armv4
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endif
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$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
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$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S
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@ -8,6 +8,10 @@
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#include <asm/assembler.h>
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#include <asm/delay.h>
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#ifdef CONFIG_ARCH_RPC
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.arch armv4
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#endif
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.text
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.LC0: .word loops_per_jiffy
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@ -14,9 +14,6 @@ obj-$(CONFIG_SOC_SAMV7) += samv7.o
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# Power Management
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obj-$(CONFIG_ATMEL_PM) += pm.o pm_suspend.o
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ifeq ($(CONFIG_CPU_V7),y)
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AFLAGS_pm_suspend.o := -march=armv7-a
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endif
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ifeq ($(CONFIG_PM_DEBUG),y)
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CFLAGS_pm.o += -DDEBUG
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endif
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@ -12,6 +12,10 @@
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#include "pm.h"
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#include "pm_data-offsets.h"
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#ifdef CONFIG_CPU_V7
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.arch armv7-a
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#endif
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#define SRAMC_SELF_FRESH_ACTIVE 0x01
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#define SRAMC_SELF_FRESH_EXIT 0x00
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@ -34,7 +34,6 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
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obj-$(CONFIG_HAVE_IMX_SRC) += src.o
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ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),)
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AFLAGS_headsmp.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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endif
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@ -48,12 +47,10 @@ obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
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obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
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ifeq ($(CONFIG_SUSPEND),y)
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AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
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obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
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endif
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ifeq ($(CONFIG_ARM_CPU_SUSPEND),y)
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AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
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endif
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obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
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@ -8,6 +8,8 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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.arch armv7-a
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diag_reg_offset:
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.word g_diag_reg - .
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@ -9,6 +9,8 @@
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#include <asm/hardware/cache-l2x0.h>
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#include "hardware.h"
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.arch armv7-a
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/*
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* The following code must assume it is running from physical address
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* where absolute virtual addresses to the data section have to be
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@ -9,6 +9,8 @@
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#include <asm/hardware/cache-l2x0.h>
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#include "hardware.h"
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.arch armv7-a
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/*
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* ==================== low level suspend ====================
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*
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@ -1,9 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include
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AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
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CFLAGS_pmsu.o := -march=armv7-a
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obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o
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ifeq ($(CONFIG_MACH_MVEBU_V7),y)
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@ -20,6 +20,7 @@
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#include <asm/assembler.h>
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#include <asm/cp15.h>
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.arch armv7-a
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.text
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/*
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* Returns the coherency base address in r1 (r0 is untouched), or 0 if
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@ -291,6 +291,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
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/* Test the CR_C bit and set it if it was cleared */
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asm volatile(
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".arch armv7-a\n\t"
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"mrc p15, 0, r0, c1, c0, 0 \n\t"
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"tst r0, %0 \n\t"
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"orreq r0, r0, #(1 << 2) \n\t"
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@ -1,6 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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AFLAGS_headsmp.o += -march=armv7-a
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obj-$(CONFIG_ARCH_WPCM450) += wpcm450.o
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obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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@ -6,6 +6,8 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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.arch armv7-a
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/*
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* The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
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* here.
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@ -1,6 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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asflags-y += -march=armv7-a
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obj-y += io.o
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obj-y += irq.o
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obj-y += pm.o
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@ -19,6 +19,8 @@
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#define PMC_SCRATCH41 0x140
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.arch armv7-a
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_resume
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@ -47,6 +47,8 @@
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#define PLLM_STORE_MASK (1 << 1)
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#define PLLP_STORE_MASK (1 << 2)
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.arch armv7-a
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.macro test_pll_state, rd, test_mask
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ldr \rd, tegra_pll_state
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tst \rd, #\test_mask
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@ -78,6 +78,8 @@
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#define PLLX_STORE_MASK (1 << 4)
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#define PLLM_PMC_STORE_MASK (1 << 5)
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.arch armv7-a
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.macro emc_device_mask, rd, base
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ldr \rd, [\base, #EMC_ADR_CFG]
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tst \rd, #0x1
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@ -22,6 +22,8 @@
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#define CLK_RESET_CCLK_BURST 0x20
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#define CLK_RESET_CCLK_DIVIDER 0x24
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.arch armv7-a
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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/*
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* tegra_disable_clean_inv_dcache
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@ -33,9 +33,6 @@ obj-$(CONFIG_CPU_ABRT_EV5TJ) += abort-ev5tj.o
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obj-$(CONFIG_CPU_ABRT_EV6) += abort-ev6.o
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obj-$(CONFIG_CPU_ABRT_EV7) += abort-ev7.o
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AFLAGS_abort-ev6.o :=-Wa,-march=armv6k
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AFLAGS_abort-ev7.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o
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obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o
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obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
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@ -49,10 +46,6 @@ obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
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obj-$(CONFIG_CPU_CACHE_NOP) += cache-nop.o
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obj-$(CONFIG_CPU_CACHE_V7M) += cache-v7m.o
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AFLAGS_cache-v6.o :=-Wa,-march=armv6
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AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
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AFLAGS_cache-v7m.o :=-Wa,-march=armv7-m
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obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
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obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
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obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o
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@ -62,8 +55,6 @@ obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
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obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
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obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o
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CFLAGS_copypage-feroceon.o := -march=armv5te
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obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
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obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
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obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
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@ -72,9 +63,6 @@ obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o
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obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o
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obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o
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AFLAGS_tlb-v6.o :=-Wa,-march=armv6
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AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
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obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
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obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
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@ -101,9 +89,6 @@ obj-$(CONFIG_CPU_V6K) += proc-v6.o
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obj-$(CONFIG_CPU_V7) += proc-v7.o proc-v7-bugs.o
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obj-$(CONFIG_CPU_V7M) += proc-v7m.o
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AFLAGS_proc-v6.o :=-Wa,-march=armv6
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AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_OUTER_CACHE) += l2c-common.o
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obj-$(CONFIG_CACHE_B15_RAC) += cache-b15-rac.o
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obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
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@ -16,6 +16,7 @@
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* abort here if the I-TLB and D-TLB aren't seeing the same
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* picture. Unfortunately, this does happen. We live with it.
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*/
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.arch armv6k
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.align 5
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ENTRY(v6_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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*
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* Purpose : obtain information about current aborted instruction.
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*/
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.arch armv7-a
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.align 5
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ENTRY(v7_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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@ -19,6 +19,8 @@
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#define D_CACHE_LINE_SIZE 32
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#define BTB_FLUSH_SIZE 8
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.arch armv6
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/*
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* v6_flush_icache_all()
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*
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@ -16,6 +16,8 @@
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#include "proc-macros.S"
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.arch armv7-a
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#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
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.globl icache_size
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.data
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@ -18,6 +18,8 @@
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#include "proc-macros.S"
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.arch armv7-m
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/* Generic V7M read/write macros for memory mapped cache operations */
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.macro v7m_cache_read, rt, reg
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movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
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@ -15,6 +15,7 @@ static void feroceon_copy_user_page(void *kto, const void *kfrom)
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int tmp;
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asm volatile ("\
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.arch armv5te \n\
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1: ldmia %1!, {r2 - r7, ip, lr} \n\
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pld [%1, #0] \n\
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pld [%1, #32] \n\
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@ -32,6 +32,8 @@
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#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
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#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
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.arch armv6
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ENTRY(cpu_v6_proc_init)
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ret lr
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@ -24,6 +24,8 @@
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#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
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#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
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.arch armv7-a
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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@ -24,6 +24,8 @@
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#include "proc-v7-2level.S"
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#endif
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.arch armv7-a
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ENTRY(cpu_v7_proc_init)
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ret lr
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ENDPROC(cpu_v7_proc_init)
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@ -17,6 +17,8 @@
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#define HARVARD_TLB
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.arch armv6
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/*
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* v6wbi_flush_user_tlb_range(start, end, vma)
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*
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@ -16,6 +16,8 @@
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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.arch armv7-a
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/*
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* v7wbi_flush_user_tlb_range(start, end, vma)
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*
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@ -32,8 +32,6 @@ obj-$(CONFIG_FPGA_DFL_EMIF) += dfl-emif.o
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||||
|
||||
ti-emif-sram-objs := ti-emif-pm.o ti-emif-sram-pm.o
|
||||
|
||||
AFLAGS_ti-emif-sram-pm.o :=-Wa,-march=armv7-a
|
||||
|
||||
$(obj)/ti-emif-sram-pm.o: $(obj)/ti-emif-asm-offsets.h
|
||||
|
||||
$(obj)/ti-emif-asm-offsets.h: $(obj)/emif-asm-offsets.s FORCE
|
||||
|
@ -28,6 +28,7 @@
|
||||
|
||||
.arm
|
||||
.align 3
|
||||
.arch armv7-a
|
||||
|
||||
ENTRY(ti_emif_sram)
|
||||
|
||||
|
@ -1,4 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_ARM) += s2-arm.o pm-arm.o
|
||||
AFLAGS_s2-arm.o := -march=armv7-a
|
||||
obj-$(CONFIG_BMIPS_GENERIC) += s2-mips.o s3-mips.o pm-mips.o
|
||||
|
@ -8,6 +8,7 @@
|
||||
|
||||
#include "pm.h"
|
||||
|
||||
.arch armv7-a
|
||||
.text
|
||||
.align 3
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user