remoteproc: mediatek: Extract SCP common registers
This is the 1st preliminary steps for probing multi-core SCP. The registers of config and l1tcm are common on single-core SCP and multi-core SCP. Extract these registers out to reduce duplicated fields in mtk_scp when multiple SCP instances are created. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-6-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
parent
6a1c9aaf04
commit
9ea166698f
@ -100,17 +100,20 @@ struct mtk_scp_of_data {
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size_t ipi_buf_offset;
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};
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struct mtk_scp_of_cluster {
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void __iomem *reg_base;
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void __iomem *l1tcm_base;
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size_t l1tcm_size;
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phys_addr_t l1tcm_phys;
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};
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struct mtk_scp {
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struct device *dev;
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struct rproc *rproc;
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struct clk *clk;
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void __iomem *reg_base;
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void __iomem *sram_base;
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size_t sram_size;
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phys_addr_t sram_phys;
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void __iomem *l1tcm_base;
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size_t l1tcm_size;
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phys_addr_t l1tcm_phys;
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const struct mtk_scp_of_data *data;
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@ -128,6 +131,8 @@ struct mtk_scp {
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size_t dram_size;
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struct rproc_subdev *rpmsg_subdev;
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struct mtk_scp_of_cluster *cluster;
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};
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/**
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@ -152,45 +152,45 @@ static void mt8183_scp_reset_assert(struct mtk_scp *scp)
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{
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u32 val;
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val = readl(scp->reg_base + MT8183_SW_RSTN);
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val = readl(scp->cluster->reg_base + MT8183_SW_RSTN);
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val &= ~MT8183_SW_RSTN_BIT;
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writel(val, scp->reg_base + MT8183_SW_RSTN);
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writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
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}
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static void mt8183_scp_reset_deassert(struct mtk_scp *scp)
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{
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u32 val;
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val = readl(scp->reg_base + MT8183_SW_RSTN);
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val = readl(scp->cluster->reg_base + MT8183_SW_RSTN);
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val |= MT8183_SW_RSTN_BIT;
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writel(val, scp->reg_base + MT8183_SW_RSTN);
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writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
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}
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static void mt8192_scp_reset_assert(struct mtk_scp *scp)
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{
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writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
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writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
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}
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static void mt8192_scp_reset_deassert(struct mtk_scp *scp)
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{
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writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR);
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writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_CLR);
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}
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static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp)
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{
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writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET);
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writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_SET);
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}
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static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp)
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{
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writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR);
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writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_CLR);
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}
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static void mt8183_scp_irq_handler(struct mtk_scp *scp)
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{
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u32 scp_to_host;
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scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST);
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scp_to_host = readl(scp->cluster->reg_base + MT8183_SCP_TO_HOST);
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if (scp_to_host & MT8183_SCP_IPC_INT_BIT)
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scp_ipi_handler(scp);
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else
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@ -198,14 +198,14 @@ static void mt8183_scp_irq_handler(struct mtk_scp *scp)
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/* SCP won't send another interrupt until we set SCP_TO_HOST to 0. */
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writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT,
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scp->reg_base + MT8183_SCP_TO_HOST);
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scp->cluster->reg_base + MT8183_SCP_TO_HOST);
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}
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static void mt8192_scp_irq_handler(struct mtk_scp *scp)
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{
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u32 scp_to_host;
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scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET);
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scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET);
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if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
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scp_ipi_handler(scp);
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@ -215,10 +215,10 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
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* MT8192_SCP2APMCU_IPC.
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*/
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writel(MT8192_SCP_IPC_INT_BIT,
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scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
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scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
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} else {
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scp_wdt_handler(scp, scp_to_host);
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writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ);
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writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
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}
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}
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@ -226,12 +226,12 @@ static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp)
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{
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u32 scp_to_host;
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scp_to_host = readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET);
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scp_to_host = readl(scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_SET);
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if (scp_to_host & MT8192_SCP_IPC_INT_BIT)
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scp_ipi_handler(scp);
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writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR);
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writel(scp_to_host, scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_CLR);
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}
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static irqreturn_t scp_irq_handler(int irq, void *priv)
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@ -363,26 +363,26 @@ static int mt8195_scp_clk_get(struct mtk_scp *scp)
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static int mt8183_scp_before_load(struct mtk_scp *scp)
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{
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/* Clear SCP to host interrupt */
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writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
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writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST);
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/* Reset clocks before loading FW */
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writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
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writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL);
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/* Initialize TCM before loading FW. */
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writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
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writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
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/* Turn on the power of SCP's SRAM before using it. */
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writel(0x0, scp->reg_base + MT8183_SCP_SRAM_PDN);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_SRAM_PDN);
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/*
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* Set I-cache and D-cache size before loading SCP FW.
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* SCP SRAM logical address may change when cache size setting differs.
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*/
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writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
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scp->reg_base + MT8183_SCP_CACHE_CON);
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writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
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scp->cluster->reg_base + MT8183_SCP_CACHE_CON);
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writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON);
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return 0;
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}
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@ -408,28 +408,28 @@ static void scp_sram_power_off(void __iomem *addr, u32 reserved_mask)
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static int mt8186_scp_before_load(struct mtk_scp *scp)
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{
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/* Clear SCP to host interrupt */
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writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
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writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST);
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/* Reset clocks before loading FW */
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writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
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writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL);
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/* Turn on the power of SCP's SRAM before using it. Enable 1 block per time*/
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scp_sram_power_on(scp->reg_base + MT8183_SCP_SRAM_PDN, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8183_SCP_SRAM_PDN, 0);
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/* Initialize TCM before loading FW. */
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writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
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writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
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writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
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writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD);
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writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
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writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
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writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
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/*
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* Set I-cache and D-cache size before loading SCP FW.
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* SCP SRAM logical address may change when cache size setting differs.
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*/
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writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
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scp->reg_base + MT8183_SCP_CACHE_CON);
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writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
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scp->cluster->reg_base + MT8183_SCP_CACHE_CON);
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writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON);
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return 0;
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}
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@ -437,19 +437,19 @@ static int mt8186_scp_before_load(struct mtk_scp *scp)
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static int mt8192_scp_before_load(struct mtk_scp *scp)
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{
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/* clear SPM interrupt, SCP2SPM_IPC_CLR */
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writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
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writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
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writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
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writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
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/* enable SRAM clock */
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
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scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
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/* enable MPU for all memory regions */
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writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
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writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
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return 0;
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}
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@ -457,20 +457,20 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
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static int mt8195_scp_before_load(struct mtk_scp *scp)
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{
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/* clear SPM interrupt, SCP2SPM_IPC_CLR */
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writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
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writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
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writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
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writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
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/* enable SRAM clock */
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN,
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MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
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scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
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/* enable MPU for all memory regions */
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writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
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writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
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return 0;
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}
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@ -479,10 +479,10 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp)
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{
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scp->data->scp_reset_assert(scp);
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scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0);
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/* enable MPU for all memory regions */
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writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
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writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
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return 0;
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}
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@ -601,11 +601,11 @@ static void *mt8192_scp_da_to_va(struct mtk_scp *scp, u64 da, size_t len)
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}
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/* optional memory region */
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if (scp->l1tcm_size &&
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da >= scp->l1tcm_phys &&
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(da + len) <= scp->l1tcm_phys + scp->l1tcm_size) {
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offset = da - scp->l1tcm_phys;
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return (void __force *)scp->l1tcm_base + offset;
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if (scp->cluster->l1tcm_size &&
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da >= scp->cluster->l1tcm_phys &&
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(da + len) <= scp->cluster->l1tcm_phys + scp->cluster->l1tcm_size) {
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offset = da - scp->cluster->l1tcm_phys;
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return (void __force *)scp->cluster->l1tcm_base + offset;
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}
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/* optional memory region */
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@ -629,43 +629,43 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iome
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static void mt8183_scp_stop(struct mtk_scp *scp)
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{
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/* Disable SCP watchdog */
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writel(0, scp->reg_base + MT8183_WDT_CFG);
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writel(0, scp->cluster->reg_base + MT8183_WDT_CFG);
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}
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static void mt8192_scp_stop(struct mtk_scp *scp)
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{
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/* Disable SRAM clock */
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
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scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
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scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
|
||||
|
||||
/* Disable SCP watchdog */
|
||||
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
|
||||
writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
|
||||
}
|
||||
|
||||
static void mt8195_scp_stop(struct mtk_scp *scp)
|
||||
{
|
||||
/* Disable SRAM clock */
|
||||
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
|
||||
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
|
||||
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
|
||||
scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN,
|
||||
MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
|
||||
scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
|
||||
|
||||
/* Disable SCP watchdog */
|
||||
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
|
||||
writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
|
||||
}
|
||||
|
||||
static void mt8195_scp_c1_stop(struct mtk_scp *scp)
|
||||
{
|
||||
/* Power off CPU SRAM */
|
||||
scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0);
|
||||
scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0);
|
||||
|
||||
/* Disable SCP watchdog */
|
||||
writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG);
|
||||
writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG);
|
||||
}
|
||||
|
||||
static int scp_stop(struct rproc *rproc)
|
||||
@ -859,11 +859,16 @@ static int scp_probe(struct platform_device *pdev)
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct mtk_scp *scp;
|
||||
struct mtk_scp_of_cluster *scp_cluster;
|
||||
struct rproc *rproc;
|
||||
struct resource *res;
|
||||
const char *fw_name = "scp.img";
|
||||
int ret, i;
|
||||
|
||||
scp_cluster = devm_kzalloc(dev, sizeof(*scp_cluster), GFP_KERNEL);
|
||||
if (!scp_cluster)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = rproc_of_parse_firmware(dev, 0, &fw_name);
|
||||
if (ret < 0 && ret != -EINVAL)
|
||||
return ret;
|
||||
@ -876,6 +881,7 @@ static int scp_probe(struct platform_device *pdev)
|
||||
scp->rproc = rproc;
|
||||
scp->dev = dev;
|
||||
scp->data = of_device_get_match_data(dev);
|
||||
scp->cluster = scp_cluster;
|
||||
platform_set_drvdata(pdev, scp);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
|
||||
@ -889,20 +895,20 @@ static int scp_probe(struct platform_device *pdev)
|
||||
|
||||
/* l1tcm is an optional memory region */
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm");
|
||||
scp->l1tcm_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(scp->l1tcm_base)) {
|
||||
ret = PTR_ERR(scp->l1tcm_base);
|
||||
scp->cluster->l1tcm_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(scp->cluster->l1tcm_base)) {
|
||||
ret = PTR_ERR(scp->cluster->l1tcm_base);
|
||||
if (ret != -EINVAL) {
|
||||
return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n");
|
||||
}
|
||||
} else {
|
||||
scp->l1tcm_size = resource_size(res);
|
||||
scp->l1tcm_phys = res->start;
|
||||
scp->cluster->l1tcm_size = resource_size(res);
|
||||
scp->cluster->l1tcm_phys = res->start;
|
||||
}
|
||||
|
||||
scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
|
||||
if (IS_ERR(scp->reg_base))
|
||||
return dev_err_probe(dev, PTR_ERR(scp->reg_base),
|
||||
scp->cluster->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
|
||||
if (IS_ERR(scp->cluster->reg_base))
|
||||
return dev_err_probe(dev, PTR_ERR(scp->cluster->reg_base),
|
||||
"Failed to parse and map cfg memory\n");
|
||||
|
||||
ret = scp->data->scp_clk_get(scp);
|
||||
|
@ -177,7 +177,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
|
||||
mutex_lock(&scp->send_lock);
|
||||
|
||||
/* Wait until SCP receives the last command */
|
||||
ret = readl_poll_timeout_atomic(scp->reg_base + scp->data->host_to_scp_reg,
|
||||
ret = readl_poll_timeout_atomic(scp->cluster->reg_base + scp->data->host_to_scp_reg,
|
||||
val, !val, 0, SCP_TIMEOUT_US);
|
||||
if (ret) {
|
||||
dev_err(scp->dev, "%s: IPI timeout!\n", __func__);
|
||||
@ -192,7 +192,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
|
||||
scp->ipi_id_ack[id] = false;
|
||||
/* send the command to SCP */
|
||||
writel(scp->data->host_to_scp_int_bit,
|
||||
scp->reg_base + scp->data->host_to_scp_reg);
|
||||
scp->cluster->reg_base + scp->data->host_to_scp_reg);
|
||||
|
||||
if (wait) {
|
||||
/* wait for SCP's ACK */
|
||||
|
Loading…
Reference in New Issue
Block a user