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docs: PCI: Fix typos

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Fix typos in PCI docs.

Link: https://lore.kernel.org/r/20231223184720.25645-1-tintinm2017@gmail.com
Link: https://lore.kernel.org/r/20231223184412.25598-1-tintinm2017@gmail.com
Signed-off-by: Attreyee Mukherjee <tintinm2017@gmail.com>
[bhelgaas: squashed, commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>  # for "busses" only
This commit is contained in:
attreyee-muk 2023-12-24 00:17:20 +05:30 committed by Bjorn Helgaas
parent 0942155a48
commit 9ca65c373f
2 changed files with 2 additions and 2 deletions
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2
Documentation/PCI/boot-interrupts.rst
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@ -61,7 +61,7 @@ Conditions
========== ==========
The use of threaded interrupts is the most likely condition to trigger The use of threaded interrupts is the most likely condition to trigger
this problem today. Threaded interrupts may not be reenabled after the IRQ this problem today. Threaded interrupts may not be re-enabled after the IRQ
handler wakes. These "one shot" conditions mean that the threaded interrupt handler wakes. These "one shot" conditions mean that the threaded interrupt
needs to keep the interrupt line masked until the threaded handler has run. needs to keep the interrupt line masked until the threaded handler has run.
Especially when dealing with high data rate interrupts, the thread needs to Especially when dealing with high data rate interrupts, the thread needs to

2
Documentation/PCI/msi-howto.rst
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@ -236,7 +236,7 @@ including a full 'lspci -v' so we can add the quirks to the kernel.
Disabling MSIs below a bridge Disabling MSIs below a bridge
----------------------------- -----------------------------
Some PCI bridges are not able to route MSIs between busses properly. Some PCI bridges are not able to route MSIs between buses properly.
In this case, MSIs must be disabled on all devices behind the bridge. In this case, MSIs must be disabled on all devices behind the bridge.
Some bridges allow you to enable MSIs by changing some bits in their Some bridges allow you to enable MSIs by changing some bits in their