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soundwire: intel_ace2.x: add AC timing extensions for PantherLake

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The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL
register to better control clocks/delays. These bitfields were
reserved/zero in the ACE2.x IP, to simplify the integration the new
bifields are added unconditionally. The behavior will only be impacted
when the firmware exposes DSD properties to set non-zero values.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20240603070240.5165-1-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Pierre-Louis Bossart 2024-06-03 15:02:40 +08:00 committed by Vinod Koul
parent a5b7365f28
commit 9b5fd115e7
4 changed files with 45 additions and 0 deletions
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5
drivers/soundwire/intel.h
View File

@ -59,6 +59,11 @@ struct sdw_intel {
};
struct sdw_intel_prop {
u16 clde;
u16 doaise2;
u16 dodse2;
u16 clds;
u16 clss;
u16 doaise;
u16 doais;
u16 dodse;

15
drivers/soundwire/intel_ace2x.c
View File

@ -27,6 +27,11 @@ static void intel_shim_vs_init(struct sdw_intel *sdw)
void __iomem *shim_vs = sdw->link_res->shim_vs;
struct sdw_bus *bus = &sdw->cdns.bus;
struct sdw_intel_prop *intel_prop;
u16 clde;
u16 doaise2;
u16 dodse2;
u16 clds;
u16 clss;
u16 doaise;
u16 doais;
u16 dodse;
@ -34,12 +39,22 @@ static void intel_shim_vs_init(struct sdw_intel *sdw)
u16 act;
intel_prop = bus->vendor_specific_prop;
clde = intel_prop->clde;
doaise2 = intel_prop->doaise2;
dodse2 = intel_prop->dodse2;
clds = intel_prop->clds;
clss = intel_prop->clss;
doaise = intel_prop->doaise;
doais = intel_prop->doais;
dodse = intel_prop->dodse;
dods = intel_prop->dods;
act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL);
u16p_replace_bits(&act, clde, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE);
u16p_replace_bits(&act, doaise2, SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2);
u16p_replace_bits(&act, dodse2, SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2);
u16p_replace_bits(&act, clds, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS);
u16p_replace_bits(&act, clss, SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS);
u16p_replace_bits(&act, doaise, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE);
u16p_replace_bits(&act, doais, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS);
u16p_replace_bits(&act, dodse, SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE);

20
drivers/soundwire/intel_auxdevice.c
View File

@ -159,11 +159,31 @@ static int sdw_master_read_intel_prop(struct sdw_bus *bus)
return -ENOMEM;
/* initialize with hardware defaults, in case the properties are not found */
intel_prop->clde = 0x0;
intel_prop->doaise2 = 0x0;
intel_prop->dodse2 = 0x0;
intel_prop->clds = 0x0;
intel_prop->clss = 0x0;
intel_prop->doaise = 0x1;
intel_prop->doais = 0x3;
intel_prop->dodse = 0x0;
intel_prop->dods = 0x1;
fwnode_property_read_u16(link,
"intel-sdw-clde",
&intel_prop->clde);
fwnode_property_read_u16(link,
"intel-sdw-doaise2",
&intel_prop->doaise2);
fwnode_property_read_u16(link,
"intel-sdw-dodse2",
&intel_prop->dodse2);
fwnode_property_read_u16(link,
"intel-sdw-clds",
&intel_prop->clds);
fwnode_property_read_u16(link,
"intel-sdw-clss",
&intel_prop->clss);
fwnode_property_read_u16(link,
"intel-sdw-doaise",
&intel_prop->doaise);

5
include/linux/soundwire/sdw_intel.h
View File

@ -182,6 +182,11 @@
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS BIT(6)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS GENMASK(11, 7)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2 GENMASK(13, 12)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 BIT(14)
#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE BIT(15)
/**
* struct sdw_intel_stream_params_data: configuration passed during