soundwire: intel_ace2.x: add AC timing extensions for PantherLake
The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL register to better control clocks/delays. These bitfields were reserved/zero in the ACE2.x IP, to simplify the integration the new bifields are added unconditionally. The behavior will only be impacted when the firmware exposes DSD properties to set non-zero values. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20240603070240.5165-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -59,6 +59,11 @@ struct sdw_intel {
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};
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};
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struct sdw_intel_prop {
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struct sdw_intel_prop {
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u16 clde;
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u16 doaise2;
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u16 dodse2;
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u16 clds;
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u16 clss;
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u16 doaise;
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u16 doaise;
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u16 doais;
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u16 doais;
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u16 dodse;
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u16 dodse;
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@ -27,6 +27,11 @@ static void intel_shim_vs_init(struct sdw_intel *sdw)
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void __iomem *shim_vs = sdw->link_res->shim_vs;
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void __iomem *shim_vs = sdw->link_res->shim_vs;
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struct sdw_bus *bus = &sdw->cdns.bus;
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struct sdw_bus *bus = &sdw->cdns.bus;
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struct sdw_intel_prop *intel_prop;
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struct sdw_intel_prop *intel_prop;
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u16 clde;
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u16 doaise2;
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u16 dodse2;
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u16 clds;
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u16 clss;
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u16 doaise;
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u16 doaise;
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u16 doais;
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u16 doais;
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u16 dodse;
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u16 dodse;
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@ -34,12 +39,22 @@ static void intel_shim_vs_init(struct sdw_intel *sdw)
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u16 act;
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u16 act;
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intel_prop = bus->vendor_specific_prop;
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intel_prop = bus->vendor_specific_prop;
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clde = intel_prop->clde;
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doaise2 = intel_prop->doaise2;
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dodse2 = intel_prop->dodse2;
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clds = intel_prop->clds;
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clss = intel_prop->clss;
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doaise = intel_prop->doaise;
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doaise = intel_prop->doaise;
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doais = intel_prop->doais;
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doais = intel_prop->doais;
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dodse = intel_prop->dodse;
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dodse = intel_prop->dodse;
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dods = intel_prop->dods;
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dods = intel_prop->dods;
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act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL);
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act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL);
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u16p_replace_bits(&act, clde, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE);
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u16p_replace_bits(&act, doaise2, SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2);
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u16p_replace_bits(&act, dodse2, SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2);
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u16p_replace_bits(&act, clds, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS);
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u16p_replace_bits(&act, clss, SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS);
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u16p_replace_bits(&act, doaise, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE);
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u16p_replace_bits(&act, doaise, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE);
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u16p_replace_bits(&act, doais, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS);
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u16p_replace_bits(&act, doais, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS);
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u16p_replace_bits(&act, dodse, SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE);
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u16p_replace_bits(&act, dodse, SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE);
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@ -159,11 +159,31 @@ static int sdw_master_read_intel_prop(struct sdw_bus *bus)
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return -ENOMEM;
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return -ENOMEM;
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/* initialize with hardware defaults, in case the properties are not found */
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/* initialize with hardware defaults, in case the properties are not found */
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intel_prop->clde = 0x0;
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intel_prop->doaise2 = 0x0;
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intel_prop->dodse2 = 0x0;
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intel_prop->clds = 0x0;
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intel_prop->clss = 0x0;
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intel_prop->doaise = 0x1;
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intel_prop->doaise = 0x1;
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intel_prop->doais = 0x3;
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intel_prop->doais = 0x3;
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intel_prop->dodse = 0x0;
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intel_prop->dodse = 0x0;
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intel_prop->dods = 0x1;
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intel_prop->dods = 0x1;
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fwnode_property_read_u16(link,
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"intel-sdw-clde",
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&intel_prop->clde);
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fwnode_property_read_u16(link,
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"intel-sdw-doaise2",
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&intel_prop->doaise2);
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fwnode_property_read_u16(link,
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"intel-sdw-dodse2",
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&intel_prop->dodse2);
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fwnode_property_read_u16(link,
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"intel-sdw-clds",
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&intel_prop->clds);
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fwnode_property_read_u16(link,
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"intel-sdw-clss",
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&intel_prop->clss);
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fwnode_property_read_u16(link,
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fwnode_property_read_u16(link,
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"intel-sdw-doaise",
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"intel-sdw-doaise",
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&intel_prop->doaise);
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&intel_prop->doaise);
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@ -182,6 +182,11 @@
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
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#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS BIT(6)
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#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS GENMASK(11, 7)
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#define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2 GENMASK(13, 12)
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#define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 BIT(14)
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#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE BIT(15)
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/**
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/**
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* struct sdw_intel_stream_params_data: configuration passed during
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* struct sdw_intel_stream_params_data: configuration passed during
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