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ARM: dts: stm32: add SPI support on STM32F746

Add device tree nodes for the STM32F746 SPI controllers.

Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Ben Wolsieffer 2023-11-02 15:37:22 -04:00 committed by Alexandre Torgue
parent 86f15a5a6c
commit 9a7308232a

View File

@ -274,6 +274,26 @@
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
};
spi2: spi@40003800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32f7-spi";
reg = <0x40003800 0x400>;
interrupts = <36>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
status = "disabled";
};
spi3: spi@40003c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32f7-spi";
reg = <0x40003c00 0x400>;
interrupts = <51>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
@ -491,6 +511,26 @@
status = "disabled";
};
spi1: spi@40013000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32f7-spi";
reg = <0x40013000 0x400>;
interrupts = <35>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
status = "disabled";
};
spi4: spi@40013400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32f7-spi";
reg = <0x40013400 0x400>;
interrupts = <84>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
status = "disabled";
};
syscfg: syscon@40013800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
@ -555,6 +595,26 @@
};
};
spi5: spi@40015000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32f7-spi";
reg = <0x40015000 0x400>;
interrupts = <85>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
status = "disabled";
};
spi6: spi@40015400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32f7-spi";
reg = <0x40015400 0x400>;
interrupts = <86>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
status = "disabled";
};
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;