ARM: dts: stm32: add SPI support on STM32F746
Add device tree nodes for the STM32F746 SPI controllers. Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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@ -274,6 +274,26 @@
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
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};
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spi2: spi@40003800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32f7-spi";
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reg = <0x40003800 0x400>;
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interrupts = <36>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32f7-spi";
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reg = <0x40003c00 0x400>;
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interrupts = <51>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32f7-uart";
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reg = <0x40004400 0x400>;
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@ -491,6 +511,26 @@
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status = "disabled";
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};
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spi1: spi@40013000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32f7-spi";
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reg = <0x40013000 0x400>;
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interrupts = <35>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
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status = "disabled";
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};
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spi4: spi@40013400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32f7-spi";
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reg = <0x40013400 0x400>;
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interrupts = <84>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
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status = "disabled";
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};
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syscfg: syscon@40013800 {
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compatible = "st,stm32-syscfg", "syscon";
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reg = <0x40013800 0x400>;
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@ -555,6 +595,26 @@
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};
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};
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spi5: spi@40015000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32f7-spi";
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reg = <0x40015000 0x400>;
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interrupts = <85>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
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status = "disabled";
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};
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spi6: spi@40015400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32f7-spi";
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reg = <0x40015400 0x400>;
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interrupts = <86>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
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status = "disabled";
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};
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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reg = <0x40016800 0x200>;
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