LoongArch: vDSO: Tune chacha implementation
As Christophe pointed out, tuning the chacha implementation by scheduling the instructions like what GCC does can improve the performance. The tuning does not introduce too much complexity (basically it's just reordering some instructions). And the tuning does not hurt readibility too much: actually the tuned code looks even more similar to a textbook-style implementation based on 128-bit vectors. So overall it's a good deal to me. Tested with vdso_test_getchacha and benched with vdso_test_getrandom. On a LA664 the speedup is 5%, and I expect a larger speedup on LA[2-4]64 with a lower issue rate. Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/all/77655d9e-fc05-4300-8f0d-7b2ad840d091@csgroup.eu/ Signed-off-by: Xi Ruoyao <xry111@xry111.site> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
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@ -9,23 +9,11 @@
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.text
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/* Salsa20 quarter-round */
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.macro QR a b c d
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add.w \a, \a, \b
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xor \d, \d, \a
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rotri.w \d, \d, 16
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add.w \c, \c, \d
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xor \b, \b, \c
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rotri.w \b, \b, 20
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add.w \a, \a, \b
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xor \d, \d, \a
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rotri.w \d, \d, 24
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add.w \c, \c, \d
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xor \b, \b, \c
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rotri.w \b, \b, 25
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.macro OP_4REG op d0 d1 d2 d3 s0 s1 s2 s3
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\op \d0, \d0, \s0
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\op \d1, \d1, \s1
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\op \d2, \d2, \s2
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\op \d3, \d3, \s3
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.endm
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/*
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@ -74,6 +62,23 @@ SYM_FUNC_START(__arch_chacha20_blocks_nostack)
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/* Reuse i as copy3 */
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#define copy3 i
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/* Packs to be used with OP_4REG */
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#define line0 state0, state1, state2, state3
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#define line1 state4, state5, state6, state7
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#define line2 state8, state9, state10, state11
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#define line3 state12, state13, state14, state15
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#define line1_perm state5, state6, state7, state4
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#define line2_perm state10, state11, state8, state9
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#define line3_perm state15, state12, state13, state14
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#define copy copy0, copy1, copy2, copy3
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#define _16 16, 16, 16, 16
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#define _20 20, 20, 20, 20
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#define _24 24, 24, 24, 24
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#define _25 25, 25, 25, 25
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/*
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* The ABI requires s0-s9 saved, and sp aligned to 16-byte.
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* This does not violate the stack-less requirement: no sensitive data
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@ -126,16 +131,38 @@ SYM_FUNC_START(__arch_chacha20_blocks_nostack)
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li.w i, 10
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.Lpermute:
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/* odd round */
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QR state0, state4, state8, state12
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QR state1, state5, state9, state13
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QR state2, state6, state10, state14
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QR state3, state7, state11, state15
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OP_4REG add.w line0, line1
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OP_4REG xor line3, line0
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OP_4REG rotri.w line3, _16
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OP_4REG add.w line2, line3
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OP_4REG xor line1, line2
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OP_4REG rotri.w line1, _20
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OP_4REG add.w line0, line1
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OP_4REG xor line3, line0
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OP_4REG rotri.w line3, _24
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OP_4REG add.w line2, line3
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OP_4REG xor line1, line2
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OP_4REG rotri.w line1, _25
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/* even round */
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QR state0, state5, state10, state15
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QR state1, state6, state11, state12
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QR state2, state7, state8, state13
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QR state3, state4, state9, state14
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OP_4REG add.w line0, line1_perm
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OP_4REG xor line3_perm, line0
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OP_4REG rotri.w line3_perm, _16
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OP_4REG add.w line2_perm, line3_perm
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OP_4REG xor line1_perm, line2_perm
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OP_4REG rotri.w line1_perm, _20
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OP_4REG add.w line0, line1_perm
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OP_4REG xor line3_perm, line0
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OP_4REG rotri.w line3_perm, _24
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OP_4REG add.w line2_perm, line3_perm
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OP_4REG xor line1_perm, line2_perm
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OP_4REG rotri.w line1_perm, _25
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addi.w i, i, -1
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bnez i, .Lpermute
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@ -147,10 +174,7 @@ SYM_FUNC_START(__arch_chacha20_blocks_nostack)
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li.w copy3, 0x6b206574
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/* output[0,1,2,3] = copy[0,1,2,3] + state[0,1,2,3] */
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add.w state0, state0, copy0
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add.w state1, state1, copy1
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add.w state2, state2, copy2
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add.w state3, state3, copy3
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OP_4REG add.w line0, copy
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st.w state0, output, 0
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st.w state1, output, 4
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st.w state2, output, 8
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@ -165,10 +189,7 @@ SYM_FUNC_START(__arch_chacha20_blocks_nostack)
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ld.w state3, key, 12
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/* output[4,5,6,7] = state[0,1,2,3] + state[4,5,6,7] */
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add.w state4, state4, state0
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add.w state5, state5, state1
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add.w state6, state6, state2
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add.w state7, state7, state3
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OP_4REG add.w line1, line0
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st.w state4, output, 16
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st.w state5, output, 20
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st.w state6, output, 24
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@ -181,10 +202,7 @@ SYM_FUNC_START(__arch_chacha20_blocks_nostack)
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ld.w state3, key, 28
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/* output[8,9,10,11] = state[0,1,2,3] + state[8,9,10,11] */
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add.w state8, state8, state0
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add.w state9, state9, state1
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add.w state10, state10, state2
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add.w state11, state11, state3
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OP_4REG add.w line2, line0
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st.w state8, output, 32
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st.w state9, output, 36
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st.w state10, output, 40
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