accel/habanalabs: fix register address on PDMA/EDMA idle check
The PDMA/EDMA is_idle routines didn't check the correct CORE register in order to get the accurate idle state. Moreover, it's better to make the is_idle routine more robust by adding additional checks (IS_HALTED) before announcing that the core is idle. Signed-off-by: Koby Elbaz <kelbaz@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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@ -86,10 +86,11 @@
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#define KDMA_TIMEOUT_USEC USEC_PER_SEC
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#define IS_DMA_IDLE(dma_core_idle_ind_mask) \
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(!((dma_core_idle_ind_mask) & \
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((DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK) | \
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(DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK))))
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#define IS_DMA_IDLE(dma_core_sts0) \
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(!((dma_core_sts0) & (DCORE0_EDMA0_CORE_STS0_BUSY_MASK)))
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#define IS_DMA_HALTED(dma_core_sts1) \
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((dma_core_sts1) & (DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK))
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#define IS_MME_IDLE(mme_arch_sts) (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
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@ -6677,18 +6678,18 @@ static int gaudi2_compute_reset_late_init(struct hl_device *hdev)
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static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
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struct engines_data *e)
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{
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u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_idle_ind_mask;
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u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_sts0, dma_core_sts1;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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unsigned long *mask = (unsigned long *) mask_arr;
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const char *edma_fmt = "%-6d%-6d%-9s%#-14x%#x\n";
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const char *edma_fmt = "%-6d%-6d%-9s%#-14x%#-15x%#x\n";
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bool is_idle = true, is_eng_idle;
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int engine_idx, i, j;
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u64 offset;
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if (e)
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hl_engine_data_sprintf(e,
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"\nCORE EDMA is_idle QM_GLBL_STS0 DMA_CORE_IDLE_IND_MASK\n"
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"---- ---- ------- ------------ ----------------------\n");
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"\nCORE EDMA is_idle QM_GLBL_STS0 DMA_CORE_STS0 DMA_CORE_STS1\n"
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"---- ---- ------- ------------ ------------- -------------\n");
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for (i = 0; i < NUM_OF_DCORES; i++) {
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for (j = 0 ; j < NUM_OF_EDMA_PER_DCORE ; j++) {
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@ -6701,25 +6702,23 @@ static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u
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i * GAUDI2_ENGINE_ID_DCORE_OFFSET + j;
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offset = i * DCORE_OFFSET + j * DCORE_EDMA_OFFSET;
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dma_core_idle_ind_mask =
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RREG32(mmDCORE0_EDMA0_CORE_IDLE_IND_MASK + offset);
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dma_core_sts0 = RREG32(mmDCORE0_EDMA0_CORE_STS0 + offset);
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dma_core_sts1 = RREG32(mmDCORE0_EDMA0_CORE_STS1 + offset);
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qm_glbl_sts0 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS0 + offset);
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qm_glbl_sts1 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS1 + offset);
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qm_cgm_sts = RREG32(mmDCORE0_EDMA0_QM_CGM_STS + offset);
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is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) &&
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IS_DMA_IDLE(dma_core_idle_ind_mask);
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IS_DMA_IDLE(dma_core_sts0) && !IS_DMA_HALTED(dma_core_sts1);
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is_idle &= is_eng_idle;
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if (mask && !is_eng_idle)
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set_bit(engine_idx, mask);
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if (e)
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hl_engine_data_sprintf(e, edma_fmt, i, j,
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is_eng_idle ? "Y" : "N",
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qm_glbl_sts0,
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dma_core_idle_ind_mask);
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hl_engine_data_sprintf(e, edma_fmt, i, j, is_eng_idle ? "Y" : "N",
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qm_glbl_sts0, dma_core_sts0, dma_core_sts1);
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}
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}
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@ -6729,29 +6728,30 @@ static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u
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static bool gaudi2_get_pdma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
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struct engines_data *e)
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{
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u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_idle_ind_mask;
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u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_sts0, dma_core_sts1;
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unsigned long *mask = (unsigned long *) mask_arr;
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const char *pdma_fmt = "%-6d%-9s%#-14x%#x\n";
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const char *pdma_fmt = "%-6d%-9s%#-14x%#-15x%#x\n";
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bool is_idle = true, is_eng_idle;
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int engine_idx, i;
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u64 offset;
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if (e)
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hl_engine_data_sprintf(e,
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"\nPDMA is_idle QM_GLBL_STS0 DMA_CORE_IDLE_IND_MASK\n"
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"---- ------- ------------ ----------------------\n");
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"\nPDMA is_idle QM_GLBL_STS0 DMA_CORE_STS0 DMA_CORE_STS1\n"
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"---- ------- ------------ ------------- -------------\n");
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for (i = 0 ; i < NUM_OF_PDMA ; i++) {
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engine_idx = GAUDI2_ENGINE_ID_PDMA_0 + i;
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offset = i * PDMA_OFFSET;
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dma_core_idle_ind_mask = RREG32(mmPDMA0_CORE_IDLE_IND_MASK + offset);
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dma_core_sts0 = RREG32(mmPDMA0_CORE_STS0 + offset);
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dma_core_sts1 = RREG32(mmPDMA0_CORE_STS1 + offset);
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qm_glbl_sts0 = RREG32(mmPDMA0_QM_GLBL_STS0 + offset);
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qm_glbl_sts1 = RREG32(mmPDMA0_QM_GLBL_STS1 + offset);
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qm_cgm_sts = RREG32(mmPDMA0_QM_CGM_STS + offset);
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is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) &&
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IS_DMA_IDLE(dma_core_idle_ind_mask);
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IS_DMA_IDLE(dma_core_sts0) && !IS_DMA_HALTED(dma_core_sts1);
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is_idle &= is_eng_idle;
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if (mask && !is_eng_idle)
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@ -6759,7 +6759,7 @@ static bool gaudi2_get_pdma_idle_status(struct hl_device *hdev, u64 *mask_arr, u
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if (e)
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hl_engine_data_sprintf(e, pdma_fmt, i, is_eng_idle ? "Y" : "N",
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qm_glbl_sts0, dma_core_idle_ind_mask);
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qm_glbl_sts0, dma_core_sts0, dma_core_sts1);
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}
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return is_idle;
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