LoongArch: Fix perf event id calculation
LoongArch PMCFG has 10bit event id rather than 8 bit, so fix it. Cc: stable@vger.kernel.org Signed-off-by: Jun Yi <yijun@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
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@ -271,7 +271,7 @@ static void loongarch_pmu_enable_event(struct hw_perf_event *evt, int idx)
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WARN_ON(idx < 0 || idx >= loongarch_pmu.num_counters);
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/* Make sure interrupt enabled. */
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cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
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cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base) |
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(evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE;
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cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
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@ -594,7 +594,7 @@ static struct pmu pmu = {
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static unsigned int loongarch_pmu_perf_event_encode(const struct loongarch_perf_event *pev)
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{
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return (pev->event_id & 0xff);
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return M_PERFCTL_EVENT(pev->event_id);
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}
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static const struct loongarch_perf_event *loongarch_pmu_map_general_event(int idx)
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@ -849,7 +849,7 @@ static void resume_local_counters(void)
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static const struct loongarch_perf_event *loongarch_pmu_map_raw_event(u64 config)
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{
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raw_event.event_id = config & 0xff;
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raw_event.event_id = M_PERFCTL_EVENT(config);
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return &raw_event;
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}
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