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riscv: lib: relax assembly constraints in hweight

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rd and rs don't have to be the same. In some cases where rs needs to be
saved for later usage, this will save us some mv instructions.

Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
Reviewed-by: Xiao Wang <xiao.w.wang@intel.com>
Link: https://lore.kernel.org/r/20240527092405.134967-1-dqfext@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Qingfang Deng 2024-05-27 17:24:04 +08:00 committed by Palmer Dabbelt
parent 6ad8735994
commit 93b63f68d0
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1 changed files with 4 additions and 4 deletions
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8
arch/riscv/include/asm/arch_hweight.h
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@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
asm (".option push\n" asm (".option push\n"
".option arch,+zbb\n" ".option arch,+zbb\n"
CPOPW "%0, %0\n" CPOPW "%0, %1\n"
".option pop\n" ".option pop\n"
: "+r" (w) : :); : "=r" (w) : "r" (w) :);
return w; return w;
@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
asm (".option push\n" asm (".option push\n"
".option arch,+zbb\n" ".option arch,+zbb\n"
"cpop %0, %0\n" "cpop %0, %1\n"
".option pop\n" ".option pop\n"
: "+r" (w) : :); : "=r" (w) : "r" (w) :);
return w; return w;