arm64: dts: mediatek: mt8183: Add decoder
Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com> Signed-off-by: Frederic Chen <frederic.chen@mediatek.com> Signed-off-by: Alexandre Courbot <acourbot@chromium.org> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230630151436.155586-8-nfraprado@collabora.com
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@ -2019,6 +2019,36 @@
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#clock-cells = <1>;
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};
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vcodec_dec: video-codec@16020000 {
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compatible = "mediatek,mt8183-vcodec-dec";
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reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
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<0 0x16021000 0 0x800>, /* VDEC_VLD */
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<0 0x16021800 0 0x800>, /* VDEC_TOP */
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<0 0x16022000 0 0x1000>, /* VDEC_MC */
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<0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */
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<0 0x16024000 0 0x1000>, /* VDEC_AVCMV */
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<0 0x16025000 0 0x1000>, /* VDEC_PP */
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<0 0x16026800 0 0x800>, /* VP8_VD */
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<0 0x16027000 0 0x800>, /* VP6_VD */
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<0 0x16027800 0 0x800>, /* VP8_VL */
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<0 0x16028400 0 0x400>; /* VP9_VD */
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reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
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"hwd", "hwq", "hwb", "hwg";
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interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
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<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>;
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mediatek,scp = <&scp>;
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mediatek,vdecsys = <&vdecsys>;
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power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
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clocks = <&vdecsys CLK_VDEC_VDEC>;
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clock-names = "vdec";
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt8183-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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