LoongArch: Architectural preparation for AVEC irqchip
Add architectural preparation for AVEC irqchip, including: 1. CPUCFG feature bits definition for AVEC; 2. Detection of AVEC irqchip in cpu_probe(); 3. New IPI type definition (IPI_CLEAR_VECTOR) for AVEC; 4. Provide arch_probe_nr_irqs() for large NR_IRQS; 5. Other related changes about the number of interrupts. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20240823103936.25092-2-zhangtianyang@loongson.cn
This commit is contained in:
Huacai Chen
Thomas Gleixner
parent
06fac729a6
commit
843ed9317b
@ -65,5 +65,6 @@
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#define cpu_has_guestid cpu_opt(LOONGARCH_CPU_GUESTID)
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#define cpu_has_hypervisor cpu_opt(LOONGARCH_CPU_HYPERVISOR)
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#define cpu_has_ptw cpu_opt(LOONGARCH_CPU_PTW)
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#define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT)
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#endif /* __ASM_CPU_FEATURES_H */
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@ -99,6 +99,7 @@ enum cpu_type_enum {
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#define CPU_FEATURE_GUESTID 24 /* CPU has GuestID feature */
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#define CPU_FEATURE_HYPERVISOR 25 /* CPU has hypervisor (running in VM) */
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#define CPU_FEATURE_PTW 26 /* CPU has hardware page table walker */
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#define CPU_FEATURE_AVECINT 27 /* CPU has avec interrupt */
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#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
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#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
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@ -127,5 +128,6 @@ enum cpu_type_enum {
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#define LOONGARCH_CPU_GUESTID BIT_ULL(CPU_FEATURE_GUESTID)
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#define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR)
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#define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW)
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#define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT)
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#endif /* _ASM_CPU_H */
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@ -12,12 +12,13 @@
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extern void ack_bad_irq(unsigned int irq);
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#define ack_bad_irq ack_bad_irq
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#define NR_IPI 3
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#define NR_IPI 4
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enum ipi_msg_type {
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IPI_RESCHEDULE,
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IPI_CALL_FUNCTION,
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IPI_IRQ_WORK,
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IPI_CLEAR_VECTOR,
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};
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typedef struct {
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@ -39,11 +39,22 @@ void spurious_interrupt(void);
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#define NR_IRQS_LEGACY 16
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/*
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* 256 Vectors Mapping for AVECINTC:
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*
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* 0 - 15: Mapping classic IPs, e.g. IP0-12.
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* 16 - 255: Mapping vectors for external IRQ.
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*
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*/
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#define NR_VECTORS 256
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#define NR_LEGACY_VECTORS 16
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#define IRQ_MATRIX_BITS NR_VECTORS
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#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
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void arch_trigger_cpumask_backtrace(const struct cpumask *mask, int exclude_cpu);
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#define MAX_IO_PICS 2
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#define NR_IRQS (64 + (256 * MAX_IO_PICS))
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#define NR_IRQS (64 + NR_VECTORS * (NR_CPUS + MAX_IO_PICS))
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struct acpi_vector_group {
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int node;
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@ -65,7 +76,7 @@ extern struct acpi_vector_group msi_group[MAX_IO_PICS];
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#define LOONGSON_LPC_LAST_IRQ (LOONGSON_LPC_IRQ_BASE + 15)
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#define LOONGSON_CPU_IRQ_BASE 16
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#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 14)
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#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 15)
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#define LOONGSON_PCH_IRQ_BASE 64
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#define LOONGSON_PCH_ACPI_IRQ (LOONGSON_PCH_IRQ_BASE + 47)
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@ -253,8 +253,8 @@
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#define CSR_ESTAT_EXC_WIDTH 6
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#define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
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#define CSR_ESTAT_IS_SHIFT 0
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#define CSR_ESTAT_IS_WIDTH 14
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#define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT)
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#define CSR_ESTAT_IS_WIDTH 15
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#define CSR_ESTAT_IS (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
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#define LOONGARCH_CSR_ERA 0x6 /* ERA */
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@ -649,6 +649,13 @@
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#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
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#define LOONGARCH_CSR_ISR0 0xa0
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#define LOONGARCH_CSR_ISR1 0xa1
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#define LOONGARCH_CSR_ISR2 0xa2
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#define LOONGARCH_CSR_ISR3 0xa3
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#define LOONGARCH_CSR_IRR 0xa4
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#define LOONGARCH_CSR_PRID 0xc0
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/* Shadow MCSR : 0xc0 ~ 0xff */
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@ -1011,7 +1018,7 @@
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/*
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* CSR_ECFG IM
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*/
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#define ECFG0_IM 0x00001fff
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#define ECFG0_IM 0x00005fff
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#define ECFGB_SIP0 0
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#define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0)
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#define ECFGB_SIP1 1
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@ -1054,6 +1061,7 @@
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#define IOCSRF_EIODECODE BIT_ULL(9)
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#define IOCSRF_FLATMODE BIT_ULL(10)
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#define IOCSRF_VM BIT_ULL(11)
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#define IOCSRF_AVEC BIT_ULL(15)
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#define LOONGARCH_IOCSR_VENDOR 0x10
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@ -1065,6 +1073,7 @@
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#define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10)
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#define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21)
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#define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48)
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#define IOCSR_MISC_FUNC_AVEC_EN BIT_ULL(51)
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#define LOONGARCH_IOCSR_CPUTEMP 0x428
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@ -1387,9 +1396,10 @@ __BUILD_CSR_OP(tlbidx)
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#define INT_TI 11 /* Timer */
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#define INT_IPI 12
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#define INT_NMI 13
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#define INT_AVEC 14
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/* ExcCodes corresponding to interrupts */
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#define EXCCODE_INT_NUM (INT_NMI + 1)
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#define EXCCODE_INT_NUM (INT_AVEC + 1)
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#define EXCCODE_INT_START 64
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#define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
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@ -70,10 +70,12 @@ extern int __cpu_logical_map[NR_CPUS];
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#define ACTION_RESCHEDULE 1
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#define ACTION_CALL_FUNCTION 2
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#define ACTION_IRQ_WORK 3
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#define ACTION_CLEAR_VECTOR 4
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#define SMP_BOOT_CPU BIT(ACTION_BOOT_CPU)
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#define SMP_RESCHEDULE BIT(ACTION_RESCHEDULE)
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#define SMP_CALL_FUNCTION BIT(ACTION_CALL_FUNCTION)
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#define SMP_IRQ_WORK BIT(ACTION_IRQ_WORK)
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#define SMP_CLEAR_VECTOR BIT(ACTION_CLEAR_VECTOR)
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struct secondary_data {
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unsigned long stack;
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@ -106,7 +106,6 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
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elf_hwcap |= HWCAP_LOONGARCH_CRC32;
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}
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config = read_cpucfg(LOONGARCH_CPUCFG2);
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if (config & CPUCFG2_LAM) {
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c->options |= LOONGARCH_CPU_LAM;
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@ -174,6 +173,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
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c->options |= LOONGARCH_CPU_FLATMODE;
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if (config & IOCSRF_EIODECODE)
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c->options |= LOONGARCH_CPU_EIODECODE;
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if (config & IOCSRF_AVEC)
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c->options |= LOONGARCH_CPU_AVECINT;
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if (config & IOCSRF_VM)
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c->options |= LOONGARCH_CPU_HYPERVISOR;
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@ -87,6 +87,18 @@ static void __init init_vec_parent_group(void)
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acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
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}
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int __init arch_probe_nr_irqs(void)
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{
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int nr_io_pics = bitmap_weight(loongson_sysconf.cores_io_master, NR_CPUS);
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if (!cpu_has_avecint)
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nr_irqs = (64 + NR_VECTORS * nr_io_pics);
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else
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nr_irqs = (64 + NR_VECTORS * (nr_cpu_ids + nr_io_pics));
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return NR_IRQS_LEGACY;
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}
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void __init init_IRQ(void)
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{
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int i;
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