1

crypto: octeontx2 - add devlink option to set t106 mode

On CN10KA B0/CN10KB, CPT scatter gather format has modified
to support multi-seg in inline IPsec. Due to this CPT requires
new firmware and doesn't work with CN10KA0/A1 firmware. To make
HW works in backward compatibility mode or works with CN10KA0/A1
firmware, a bit(T106_MODE) is introduced in HW CSR.

This patch adds devlink parameter for configuring T106_MODE.
This patch also documents the devlink parameter under
Documentation/crypto/device_drivers.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Srujana Challa 2023-12-13 13:00:49 +05:30 committed by Herbert Xu
parent 92508e7fcf
commit 82f89f1aa6
6 changed files with 87 additions and 4 deletions

View File

@ -0,0 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0
Hardware Device Driver Specific Documentation
---------------------------------------------
.. toctree::
:maxdepth: 1
octeontx2

View File

@ -0,0 +1,25 @@
.. SPDX-License-Identifier: GPL-2.0
=========================
octeontx2 devlink support
=========================
This document describes the devlink features implemented by the ``octeontx2 CPT``
device drivers.
Parameters
==========
The ``octeontx2`` driver implements the following driver-specific parameters.
.. list-table:: Driver-specific parameters implemented
:widths: 5 5 5 85
* - Name
- Type
- Mode
- Description
* - ``t106_mode``
- u8
- runtime
- Used to configure CN10KA B0/CN10KB CPT to work as CN10KA A0/A1.

View File

@ -28,3 +28,4 @@ for cryptographic use cases, as well as programming examples.
api
api-samples
descore-readme
device_drivers/index

View File

@ -187,6 +187,14 @@ static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
}
static inline bool cpt_feature_sgv2(struct pci_dev *pdev)
{
if (!is_dev_otx2(pdev) && !is_dev_cn10ka_ax(pdev))
return true;
return false;
}
int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);

View File

@ -23,11 +23,46 @@ static int otx2_cpt_dl_egrp_delete(struct devlink *dl, u32 id,
static int otx2_cpt_dl_uc_info(struct devlink *dl, u32 id,
struct devlink_param_gset_ctx *ctx)
{
ctx->val.vstr[0] = '\0';
return 0;
}
static int otx2_cpt_dl_t106_mode_get(struct devlink *dl, u32 id,
struct devlink_param_gset_ctx *ctx)
{
struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
struct pci_dev *pdev = cptpf->pdev;
u64 reg_val = 0;
otx2_cpt_print_uc_dbg_info(cptpf);
otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,
BLKADDR_CPT0);
ctx->val.vu8 = (reg_val >> 18) & 0x1;
return 0;
}
static int otx2_cpt_dl_t106_mode_set(struct devlink *dl, u32 id,
struct devlink_param_gset_ctx *ctx)
{
struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
struct pci_dev *pdev = cptpf->pdev;
u64 reg_val = 0;
if (cptpf->enabled_vfs != 0 || cptpf->eng_grps.is_grps_created)
return -EPERM;
if (cpt_feature_sgv2(pdev)) {
otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,
&reg_val, BLKADDR_CPT0);
reg_val &= ~(0x1ULL << 18);
reg_val |= ((u64)ctx->val.vu8 & 0x1) << 18;
return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev,
CPT_AF_CTL, reg_val, BLKADDR_CPT0);
}
return 0;
}
@ -36,6 +71,7 @@ enum otx2_cpt_dl_param_id {
OTX2_CPT_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE,
OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE,
OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE,
};
static const struct devlink_param otx2_cpt_dl_params[] = {
@ -49,6 +85,11 @@ static const struct devlink_param otx2_cpt_dl_params[] = {
BIT(DEVLINK_PARAM_CMODE_RUNTIME),
otx2_cpt_dl_uc_info, otx2_cpt_dl_egrp_delete,
NULL),
DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE,
"t106_mode", DEVLINK_PARAM_TYPE_U8,
BIT(DEVLINK_PARAM_CMODE_RUNTIME),
otx2_cpt_dl_t106_mode_get, otx2_cpt_dl_t106_mode_set,
NULL),
};
static int otx2_cpt_dl_info_firmware_version_put(struct devlink_info_req *req,
@ -120,7 +161,6 @@ int otx2_cpt_register_dl(struct otx2_cptpf_dev *cptpf)
devlink_free(dl);
return ret;
}
devlink_register(dl);
return 0;

View File

@ -600,10 +600,10 @@ static void cptpf_get_rid(struct pci_dev *pdev, struct otx2_cptpf_dev *cptpf)
}
otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,
BLKADDR_CPT0);
if ((is_dev_cn10ka_b0(pdev) && (reg_val & BIT_ULL(18))) ||
if ((cpt_feature_sgv2(pdev) && (reg_val & BIT_ULL(18))) ||
is_dev_cn10ka_ax(pdev))
eng_grps->rid = CPT_UC_RID_CN10K_A;
else if (is_dev_cn10kb(pdev) || is_dev_cn10ka_b0(pdev))
else if (cpt_feature_sgv2(pdev))
eng_grps->rid = CPT_UC_RID_CN10K_B;
}