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soundwire: bus: extend base clock checks to 96 MHz

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Starting with MeteorLake, the input frequency to the SoundWire IP can
be 96MHz. The existing code is limited to 24MHz, change accordingly
and move branch after the 32MHz case to avoid issues.

While we're at it, reorder the frequencies by increasing order.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20240326092030.1062802-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Pierre-Louis Bossart 2024-03-26 09:20:25 +00:00 committed by Vinod Koul
parent 8292c815bb
commit 7eca9c722e
1 changed files with 6 additions and 6 deletions
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12
drivers/soundwire/bus.c
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@ -1312,18 +1312,18 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
if (!(19200000 % mclk_freq)) { if (!(19200000 % mclk_freq)) {
mclk_freq = 19200000; mclk_freq = 19200000;
base = SDW_SCP_BASE_CLOCK_19200000_HZ; base = SDW_SCP_BASE_CLOCK_19200000_HZ;
} else if (!(24000000 % mclk_freq)) {
mclk_freq = 24000000;
base = SDW_SCP_BASE_CLOCK_24000000_HZ;
} else if (!(24576000 % mclk_freq)) {
mclk_freq = 24576000;
base = SDW_SCP_BASE_CLOCK_24576000_HZ;
} else if (!(22579200 % mclk_freq)) { } else if (!(22579200 % mclk_freq)) {
mclk_freq = 22579200; mclk_freq = 22579200;
base = SDW_SCP_BASE_CLOCK_22579200_HZ; base = SDW_SCP_BASE_CLOCK_22579200_HZ;
} else if (!(24576000 % mclk_freq)) {
mclk_freq = 24576000;
base = SDW_SCP_BASE_CLOCK_24576000_HZ;
} else if (!(32000000 % mclk_freq)) { } else if (!(32000000 % mclk_freq)) {
mclk_freq = 32000000; mclk_freq = 32000000;
base = SDW_SCP_BASE_CLOCK_32000000_HZ; base = SDW_SCP_BASE_CLOCK_32000000_HZ;
} else if (!(96000000 % mclk_freq)) {
mclk_freq = 24000000;
base = SDW_SCP_BASE_CLOCK_24000000_HZ;
} else { } else {
dev_err(&slave->dev, dev_err(&slave->dev,
"Unsupported clock base, mclk %d\n", "Unsupported clock base, mclk %d\n",