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mailbox: imx: fix RST channel support

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Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated
to include the CR register. Add the missed CR register to xcr array.

Fixes: 82ab513bae ("mailbox: imx: support RST channel")
Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com> # i.MX8qm/qxp MEK boards boot
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Peng Fan 2022-09-19 11:01:36 +08:00 committed by Jassi Brar
parent 68584e380e
commit 7e5cd064f7
1 changed files with 5 additions and 5 deletions
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10
drivers/mailbox/imx-mailbox.c
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@ -904,7 +904,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.xTR = 0x20, .xTR = 0x20,
.xRR = 0x40, .xRR = 0x40,
.xSR = {0x60, 0x60, 0x60, 0x60}, .xSR = {0x60, 0x60, 0x60, 0x60},
.xCR = {0x64, 0x64, 0x64, 0x64}, .xCR = {0x64, 0x64, 0x64, 0x64, 0x64},
}; };
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
@ -927,7 +927,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
.xTR = 0x200, .xTR = 0x200,
.xRR = 0x280, .xRR = 0x280,
.xSR = {0xC, 0x118, 0x124, 0x12C}, .xSR = {0xC, 0x118, 0x124, 0x12C},
.xCR = {0x110, 0x114, 0x120, 0x128}, .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
}; };
static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = { static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
@ -938,7 +938,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
.xTR = 0x200, .xTR = 0x200,
.xRR = 0x280, .xRR = 0x280,
.xSR = {0xC, 0x118, 0x124, 0x12C}, .xSR = {0xC, 0x118, 0x124, 0x12C},
.xCR = {0x110, 0x114, 0x120, 0x128}, .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
}; };
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
@ -949,7 +949,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.xTR = 0x0, .xTR = 0x0,
.xRR = 0x10, .xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20}, .xSR = {0x20, 0x20, 0x20, 0x20},
.xCR = {0x24, 0x24, 0x24, 0x24}, .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
}; };
static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = { static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
@ -960,7 +960,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
.xTR = 0x0, .xTR = 0x0,
.xRR = 0x10, .xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20}, .xSR = {0x20, 0x20, 0x20, 0x20},
.xCR = {0x24, 0x24, 0x24, 0x24}, .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
}; };
static const struct of_device_id imx_mu_dt_ids[] = { static const struct of_device_id imx_mu_dt_ids[] = {