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dt-bindings: misc: aspeed,ast2400-cvic: Convert to DT schema

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Address warnings such as:

    arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dtb: interrupt-controller@1e6c0080: 'valid-sources' does not match any of the regexes: 'pinctrl-[0-9]+'

and

    arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dtb: /ahb/copro-interrupt-controller@1e6c2000: failed to match any schema with compatible: ['aspeed,ast2400-cvic', 'aspeed-cvic']

Note that the conversion to DT schema causes some further warnings to
be emitted, because the Aspeed devicetrees are not in great shape. These
new warnings are resolved in a separate series:

https://lore.kernel.org/lkml/20240802-dt-warnings-bmc-dts-cleanups-v1-0-1cb1378e5fcd@codeconstruct.com.au/

Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240808-dt-warnings-irq-aspeed-dt-schema-v2-2-c2531e02633d@codeconstruct.com.au
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Andrew Jeffery 2024-08-08 13:44:25 +09:30 committed by Rob Herring (Arm)
parent b081414e23
commit 7c43f89b17
2 changed files with 60 additions and 35 deletions
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60
Documentation/devicetree/bindings/misc/aspeed,ast2400-cvic.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/aspeed,ast2400-cvic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed Coprocessor Vectored Interrupt Controller
maintainers:
- Andrew Jeffery <andrew@codeconstruct.com.au>
description:
The Aspeed AST2400 and AST2500 SoCs have a controller that provides interrupts
to the ColdFire coprocessor. It's not a normal interrupt controller and it
would be rather inconvenient to create an interrupt tree for it, as it
somewhat shares some of the same sources as the main ARM interrupt controller
but with different numbers.
The AST2500 also supports a software generated interrupt.
properties:
compatible:
items:
- enum:
- aspeed,ast2400-cvic
- aspeed,ast2500-cvic
- const: aspeed,cvic
reg:
maxItems: 1
valid-sources:
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description:
A bitmap of supported sources for the implementation.
copro-sw-interrupts:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
A list of interrupt numbers that can be used as software interrupts from
the ARM to the coprocessor.
required:
- compatible
- reg
- valid-sources
additionalProperties: false
examples:
- |
interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2500-cvic", "aspeed,cvic";
reg = <0x1e6c2000 0x80>;
valid-sources = <0xffffffff>;
copro-sw-interrupts = <1>;
};

35
Documentation/devicetree/bindings/misc/aspeed,cvic.txt
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* ASPEED AST2400 and AST2500 coprocessor interrupt controller
This file describes the bindings for the interrupt controller present
in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
ColdFire coprocessor.
It is not a normal interrupt controller and it would be rather
inconvenient to create an interrupt tree for it as it somewhat shares
some of the same sources as the main ARM interrupt controller but with
different numbers.
The AST2500 supports a SW generated interrupt
Required properties:
- reg: address and length of the register for the device.
- compatible: "aspeed,cvic" and one of:
"aspeed,ast2400-cvic"
or
"aspeed,ast2500-cvic"
- valid-sources: One cell, bitmap of supported sources for the implementation
Optional properties;
- copro-sw-interrupts: List of interrupt numbers that can be used as
SW interrupts from the ARM to the coprocessor.
(AST2500 only)
Example:
cvic: copro-interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2500-cvic";
valid-sources = <0xffffffff>;
copro-sw-interrupts = <1>;
reg = <0x1e6c2000 0x80>;
};