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locking/qspinlock: Use atomic_try_cmpxchg_relaxed() in xchg_tail()

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Use atomic_try_cmpxchg_relaxed(*ptr, &old, new) instead of
atomic_cmpxchg_relaxed (*ptr, old, new) == old in xchg_tail().

x86 CMPXCHG instruction returns success in ZF flag,
so this change saves a compare after CMPXCHG.

No functional change intended.

Since this code requires NR_CPUS >= 16k, I have tested it
by unconditionally setting _Q_PENDING_BITS to 1 in
<asm-generic/qspinlock_types.h>.

Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Waiman Long <longman@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20240321195309.484275-1-ubizjak@gmail.com
This commit is contained in:
Uros Bizjak 2024-03-21 20:52:47 +01:00 committed by Ingo Molnar
parent 21689e4bfb
commit 79a34e3d84
1 changed files with 5 additions and 8 deletions
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13
kernel/locking/qspinlock.c
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@ -220,21 +220,18 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
*/
static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
{
u32 old, new, val = atomic_read(&lock->val);
u32 old, new;
for (;;) {
new = (val & _Q_LOCKED_PENDING_MASK) | tail;
old = atomic_read(&lock->val);
do {
new = (old & _Q_LOCKED_PENDING_MASK) | tail;
/*
* We can use relaxed semantics since the caller ensures that
* the MCS node is properly initialized before updating the
* tail.
*/
old = atomic_cmpxchg_relaxed(&lock->val, val, new);
if (old == val)
break;
} while (!atomic_try_cmpxchg_relaxed(&lock->val, &old, new));
val = old;
}
return old;
}
#endif /* _Q_PENDING_BITS == 8 */