nvmem: zynqmp_nvmem: Add support to access efuse
Add support to read/write efuse memory map of ZynqMP.
Below are the offsets of ZynqMP efuse memory map
0 - SOC version(read only)
0xC - 0xFC -ZynqMP specific purpose efuses
0x100 - 0x17F - Physical Unclonable Function(PUF)
efuses repurposed as user efuses
Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
Acked-by: Kalyani Akula <Kalyani.akula@amd.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20240224114516.86365-8-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Praveen Teja Kundanala
Greg Kroah-Hartman
parent
29be47fcd6
commit
737c0c8d07
@ -4,6 +4,7 @@
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* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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@ -11,24 +12,189 @@
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#include <linux/firmware/xlnx-zynqmp.h>
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#define SILICON_REVISION_MASK 0xF
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#define P_USER_0_64_UPPER_MASK GENMASK(31, 16)
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#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)
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#define WORD_INBYTES 4
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#define SOC_VER_SIZE 0x4
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#define EFUSE_MEMORY_SIZE 0x177
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#define UNUSED_SPACE 0x8
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#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \
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EFUSE_MEMORY_SIZE)
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#define SOC_VERSION_OFFSET 0x0
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#define EFUSE_START_OFFSET 0xC
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#define EFUSE_END_OFFSET 0xFC
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#define EFUSE_PUF_START_OFFSET 0x100
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#define EFUSE_PUF_MID_OFFSET 0x140
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#define EFUSE_PUF_END_OFFSET 0x17F
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#define EFUSE_NOT_ENABLED 29
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/*
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* efuse access type
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*/
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enum efuse_access {
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EFUSE_READ = 0,
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EFUSE_WRITE
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};
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static int zynqmp_nvmem_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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/**
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* struct xilinx_efuse - the basic structure
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* @src: address of the buffer to store the data to be write/read
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* @size: read/write word count
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* @offset: read/write offset
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* @flag: 0 - represents efuse read and 1- represents efuse write
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* @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
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* 1 - represents puf user fuse row number.
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*
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* this structure stores all the required details to
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* read/write efuse memory.
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*/
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struct xilinx_efuse {
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u64 src;
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u32 size;
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u32 offset;
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enum efuse_access flag;
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u32 pufuserfuse;
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};
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static int zynqmp_efuse_access(void *context, unsigned int offset,
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void *val, size_t bytes, enum efuse_access flag,
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unsigned int pufflag)
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{
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struct device *dev = context;
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struct xilinx_efuse *efuse;
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dma_addr_t dma_addr;
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dma_addr_t dma_buf;
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size_t words = bytes / WORD_INBYTES;
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int ret;
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int value;
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char *data;
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if (bytes % WORD_INBYTES != 0) {
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dev_err(dev, "Bytes requested should be word aligned\n");
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return -EOPNOTSUPP;
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}
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if (pufflag == 0 && offset % WORD_INBYTES) {
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dev_err(dev, "Offset requested should be word aligned\n");
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return -EOPNOTSUPP;
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}
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if (pufflag == 1 && flag == EFUSE_WRITE) {
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memcpy(&value, val, bytes);
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if ((offset == EFUSE_PUF_START_OFFSET ||
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offset == EFUSE_PUF_MID_OFFSET) &&
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value & P_USER_0_64_UPPER_MASK) {
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dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER_0 & P_USER_64\n");
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return -EOPNOTSUPP;
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}
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if (offset == EFUSE_PUF_END_OFFSET &&
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(value & P_USER_127_LOWER_4_BIT_MASK)) {
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dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_127\n");
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return -EOPNOTSUPP;
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}
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}
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efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse),
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&dma_addr, GFP_KERNEL);
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if (!efuse)
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return -ENOMEM;
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data = dma_alloc_coherent(dev, sizeof(bytes),
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&dma_buf, GFP_KERNEL);
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if (!data) {
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ret = -ENOMEM;
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goto efuse_data_fail;
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}
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if (flag == EFUSE_WRITE) {
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memcpy(data, val, bytes);
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efuse->flag = EFUSE_WRITE;
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} else {
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efuse->flag = EFUSE_READ;
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}
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efuse->src = dma_buf;
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efuse->size = words;
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efuse->offset = offset;
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efuse->pufuserfuse = pufflag;
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zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret);
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if (ret != 0) {
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if (ret == EFUSE_NOT_ENABLED) {
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dev_err(dev, "efuse access is not enabled\n");
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ret = -EOPNOTSUPP;
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} else {
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dev_err(dev, "Error in efuse read %x\n", ret);
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ret = -EPERM;
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}
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goto efuse_access_err;
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}
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if (flag == EFUSE_READ)
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memcpy(val, data, bytes);
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efuse_access_err:
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dma_free_coherent(dev, sizeof(bytes),
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data, dma_buf);
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efuse_data_fail:
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dma_free_coherent(dev, sizeof(struct xilinx_efuse),
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efuse, dma_addr);
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return ret;
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}
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static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes)
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{
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struct device *dev = context;
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int ret;
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int pufflag = 0;
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int idcode;
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int version;
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ret = zynqmp_pm_get_chipid(&idcode, &version);
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if (ret < 0)
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return ret;
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if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
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pufflag = 1;
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dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
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*(int *)val = version & SILICON_REVISION_MASK;
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switch (offset) {
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/* Soc version offset is zero */
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case SOC_VERSION_OFFSET:
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if (bytes != SOC_VER_SIZE)
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return -EOPNOTSUPP;
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return 0;
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ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version);
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if (ret < 0)
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return ret;
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dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
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*(int *)val = version & SILICON_REVISION_MASK;
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break;
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/* Efuse offset starts from 0xc */
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case EFUSE_START_OFFSET ... EFUSE_END_OFFSET:
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case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET:
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ret = zynqmp_efuse_access(context, offset, val,
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bytes, EFUSE_READ, pufflag);
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break;
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default:
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*(u32 *)val = 0xDEADBEEF;
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ret = 0;
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break;
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}
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return ret;
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}
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static int zynqmp_nvmem_write(void *context,
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unsigned int offset, void *val, size_t bytes)
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{
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int pufflag = 0;
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if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET)
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return -EOPNOTSUPP;
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if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
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pufflag = 1;
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return zynqmp_efuse_access(context, offset,
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val, bytes, EFUSE_WRITE, pufflag);
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}
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static const struct of_device_id zynqmp_nvmem_match[] = {
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@ -45,11 +211,11 @@ static int zynqmp_nvmem_probe(struct platform_device *pdev)
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econfig.name = "zynqmp-nvmem";
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econfig.owner = THIS_MODULE;
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econfig.word_size = 1;
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econfig.size = 1;
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econfig.size = ZYNQMP_NVMEM_SIZE;
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econfig.dev = dev;
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econfig.add_legacy_fixed_of_cells = true;
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econfig.read_only = true;
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econfig.reg_read = zynqmp_nvmem_read;
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econfig.reg_write = zynqmp_nvmem_write;
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return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));
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}
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