firmware: qcom: scm: Add wait-queue handling logic
When the firmware (FW) supports multiple requests per VM, multiple requests
from the same/different VM can reach the firmware at the same time. Since
the firmware currently being used has limited resources, it guards them
with a resource lock and puts requests on a wait-queue internally and
signals to HLOS that it is doing so. It does this by returning a new return
value in addition to success or error: SCM_WAITQ_SLEEP. A sleeping SCM call
can be woken up by an interrupt that the FW raises.
1) SCM_WAITQ_SLEEP:
When an SCM call receives this return value instead of success
or error, FW has placed this call on a wait-queue and has signalled
HLOS to put it to non-interruptible sleep.
Along with this return value, FW also passes to HLOS `wq_ctx` -
a unique number (UID) identifying the wait-queue that it has put
the call on, internally. This is to help HLOS with its own
bookkeeping to wake this sleeping call later.
Additionally, FW also passes to HLOS `smc_call_ctx` - a UID
identifying the SCM call thus being put to sleep. This is also
for HLOS' bookkeeping to wake this call up later.
These two additional values are passed via the a1 and a2
registers.
N.B.: The "ctx" in the above UID names = "context".
The handshake mechanism that HLOS uses to talk to FW about wait-queue
operations involves two new SMC calls.
1) get_wq_ctx():
Arguments: None
Returns: wq_ctx, flags, more_pending
Get the wait-queue context, and wake up either one or all of the
sleeping SCM calls associated with that wait-queue.
Additionally, repeat this if there are more wait-queues that are
ready to have their requests woken up (`more_pending`).
2) wq_resume(smc_call_ctx):
Arguments: smc_call_ctx
HLOS needs to issue this in response to receiving an
IRQ, passing to FW the same smc_call_ctx that FW
receives from HLOS via the get_wq_ctx() call.
(The mechanism to wake a SMC call back up is described in detail below)
VM_1 VM_2 Firmware
│ │ │
│ │ │
│ │ │
│ │ │
│ REQUEST_1 │ │
├────────────────────────┼─────────────────────────────────┤
│ │ │
│ │ ┌──┼──┐
│ │ │ │ │
│ │ REQUEST_2 │ │ │
│ ├──────────────────────────────┼──┤ │
│ │ │ │ │Resource
│ │ │ │ │is busy
│ │ {WQ_SLEEP} │ │ │
│ │◄─────────────────────────────┼──┤ │
│ │ wq_ctx, smc_call_ctx │ │ │
│ │ └──┼──┘
│ REQUEST_1 COMPLETE │ │
│◄───────────────────────┼─────────────────────────────────┤
│ │ │
│ │ IRQ │
│ │◄─-------------------------------│
│ │ │
│ │ get_wq_ctx() │
│ ├────────────────────────────────►│
│ │ │
│ │ │
│ │◄────────────────────────────────┤
│ │ wq_ctx, flags, and │
│ │ more_pending │
│ │ │
│ │ │
│ │ wq_resume(smc_call_ctx) │
│ ├────────────────────────────────►│
│ │ │
│ │ │
│ │ REQUEST_2 COMPLETE │
│ │◄────────────────────────────────┤
│ │ │
│ │ │
With the exception of get_wq_ctx(), the other SMC call wq_resume() can
return WQ_SLEEP (these nested rounds of WQ_SLEEP are not shown in the
above diagram for the sake of simplicity). Therefore, introduce a new
do-while loop to handle multiple WQ_SLEEP return values for the same
parent SCM call.
Request Completion in the above diagram refers to either a success
return value (zero) or error (and not SMC_WAITQ_SLEEP)
Also add the interrupt handler that wakes up a sleeping SCM call.
Signed-off-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113161114.22607-3-quic_sibis@quicinc.com
This commit is contained in:
Guru Das Srinagesh
Bjorn Andersson
parent
afb37e2577
commit
6bf3259922
@ -52,29 +52,97 @@ static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
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} while (res->a0 == QCOM_SCM_INTERRUPTED);
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}
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static void __scm_smc_do(const struct arm_smccc_args *smc,
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struct arm_smccc_res *res, bool atomic)
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static void fill_wq_resume_args(struct arm_smccc_args *resume, u32 smc_call_ctx)
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{
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int retry_count = 0;
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memset(resume->args, 0, sizeof(resume->args[0]) * ARRAY_SIZE(resume->args));
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resume->args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
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ARM_SMCCC_SMC_64, ARM_SMCCC_OWNER_SIP,
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SCM_SMC_FNID(QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_RESUME));
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resume->args[1] = QCOM_SCM_ARGS(1);
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resume->args[2] = smc_call_ctx;
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}
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int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending)
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{
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int ret;
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struct arm_smccc_res get_wq_res;
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struct arm_smccc_args get_wq_ctx = {0};
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get_wq_ctx.args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
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ARM_SMCCC_SMC_64, ARM_SMCCC_OWNER_SIP,
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SCM_SMC_FNID(QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_GET_WQ_CTX));
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/* Guaranteed to return only success or error, no WAITQ_* */
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__scm_smc_do_quirk(&get_wq_ctx, &get_wq_res);
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ret = get_wq_res.a0;
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if (ret)
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return ret;
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*wq_ctx = get_wq_res.a1;
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*flags = get_wq_res.a2;
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*more_pending = get_wq_res.a3;
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return 0;
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}
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static int __scm_smc_do_quirk_handle_waitq(struct device *dev, struct arm_smccc_args *waitq,
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struct arm_smccc_res *res)
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{
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int ret;
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u32 wq_ctx, smc_call_ctx;
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struct arm_smccc_args resume;
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struct arm_smccc_args *smc = waitq;
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do {
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__scm_smc_do_quirk(smc, res);
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if (res->a0 == QCOM_SCM_WAITQ_SLEEP) {
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wq_ctx = res->a1;
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smc_call_ctx = res->a2;
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ret = qcom_scm_wait_for_wq_completion(wq_ctx);
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if (ret)
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return ret;
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fill_wq_resume_args(&resume, smc_call_ctx);
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smc = &resume;
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}
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} while (res->a0 == QCOM_SCM_WAITQ_SLEEP);
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return 0;
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}
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static int __scm_smc_do(struct device *dev, struct arm_smccc_args *smc,
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struct arm_smccc_res *res, bool atomic)
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{
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int ret, retry_count = 0;
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if (atomic) {
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__scm_smc_do_quirk(smc, res);
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return;
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return 0;
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}
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do {
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mutex_lock(&qcom_scm_lock);
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__scm_smc_do_quirk(smc, res);
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ret = __scm_smc_do_quirk_handle_waitq(dev, smc, res);
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mutex_unlock(&qcom_scm_lock);
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if (ret)
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return ret;
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if (res->a0 == QCOM_SCM_V2_EBUSY) {
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if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
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break;
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msleep(QCOM_SCM_EBUSY_WAIT_MS);
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}
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} while (res->a0 == QCOM_SCM_V2_EBUSY);
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return 0;
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}
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@ -83,7 +151,7 @@ int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res, bool atomic)
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{
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int arglen = desc->arginfo & 0xf;
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int i;
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int i, ret;
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dma_addr_t args_phys = 0;
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void *args_virt = NULL;
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size_t alloc_len;
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@ -135,13 +203,17 @@ int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
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}
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__scm_smc_do(&smc, &smc_res, atomic);
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/* ret error check follows after args_virt cleanup*/
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ret = __scm_smc_do(dev, &smc, &smc_res, atomic);
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if (args_virt) {
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dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
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kfree(args_virt);
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}
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if (ret)
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return ret;
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if (res) {
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res->result[0] = smc_res.a1;
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res->result[1] = smc_res.a2;
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@ -4,6 +4,8 @@
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/cpumask.h>
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#include <linux/export.h>
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#include <linux/dma-mapping.h>
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@ -13,6 +15,7 @@
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#include <linux/qcom_scm.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/reset-controller.h>
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@ -33,6 +36,7 @@ struct qcom_scm {
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struct clk *iface_clk;
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struct clk *bus_clk;
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struct icc_path *path;
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struct completion waitq_comp;
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struct reset_controller_dev reset;
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/* control access to the interconnect path */
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@ -63,6 +67,9 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = {
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BIT(2), BIT(1), BIT(4), BIT(6)
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};
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#define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0)
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#define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1)
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static const char * const qcom_scm_convention_names[] = {
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[SMC_CONVENTION_UNKNOWN] = "unknown",
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[SMC_CONVENTION_ARM_32] = "smc arm 32",
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@ -1325,11 +1332,79 @@ bool qcom_scm_is_available(void)
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}
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EXPORT_SYMBOL(qcom_scm_is_available);
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static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx)
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{
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/* FW currently only supports a single wq_ctx (zero).
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* TODO: Update this logic to include dynamic allocation and lookup of
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* completion structs when FW supports more wq_ctx values.
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*/
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if (wq_ctx != 0) {
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dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n");
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return -EINVAL;
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}
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return 0;
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}
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int qcom_scm_wait_for_wq_completion(u32 wq_ctx)
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{
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int ret;
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ret = qcom_scm_assert_valid_wq_ctx(wq_ctx);
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if (ret)
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return ret;
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wait_for_completion(&__scm->waitq_comp);
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return 0;
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}
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static int qcom_scm_waitq_wakeup(struct qcom_scm *scm, unsigned int wq_ctx)
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{
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int ret;
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ret = qcom_scm_assert_valid_wq_ctx(wq_ctx);
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if (ret)
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return ret;
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complete(&__scm->waitq_comp);
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return 0;
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}
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static irqreturn_t qcom_scm_irq_handler(int irq, void *data)
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{
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int ret;
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struct qcom_scm *scm = data;
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u32 wq_ctx, flags, more_pending = 0;
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do {
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ret = scm_get_wq_ctx(&wq_ctx, &flags, &more_pending);
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if (ret) {
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dev_err(scm->dev, "GET_WQ_CTX SMC call failed: %d\n", ret);
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goto out;
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}
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if (flags != QCOM_SMC_WAITQ_FLAG_WAKE_ONE &&
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flags != QCOM_SMC_WAITQ_FLAG_WAKE_ALL) {
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dev_err(scm->dev, "Invalid flags found for wq_ctx: %u\n", flags);
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goto out;
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}
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ret = qcom_scm_waitq_wakeup(scm, wq_ctx);
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if (ret)
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goto out;
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} while (more_pending);
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out:
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return IRQ_HANDLED;
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}
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static int qcom_scm_probe(struct platform_device *pdev)
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{
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struct qcom_scm *scm;
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unsigned long clks;
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int ret;
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int irq, ret;
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scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
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if (!scm)
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@ -1402,6 +1477,19 @@ static int qcom_scm_probe(struct platform_device *pdev)
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__scm = scm;
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__scm->dev = &pdev->dev;
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init_completion(&__scm->waitq_comp);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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if (irq != -ENXIO)
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return irq;
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} else {
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ret = devm_request_threaded_irq(__scm->dev, irq, NULL, qcom_scm_irq_handler,
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IRQF_ONESHOT, "qcom-scm", __scm);
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if (ret < 0)
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return dev_err_probe(scm->dev, ret, "Failed to request qcom-scm irq\n");
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}
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__get_convention();
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/*
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@ -60,6 +60,9 @@ struct qcom_scm_res {
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u64 result[MAX_QCOM_SCM_RETS];
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};
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int qcom_scm_wait_for_wq_completion(u32 wq_ctx);
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int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending);
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#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
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extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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enum qcom_scm_convention qcom_convention,
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@ -129,6 +132,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
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#define QCOM_SCM_SVC_WAITQ 0x24
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#define QCOM_SCM_WAITQ_RESUME 0x02
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#define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03
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/* common error codes */
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#define QCOM_SCM_V2_EBUSY -12
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#define QCOM_SCM_ENOMEM -5
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@ -137,6 +144,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
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#define QCOM_SCM_EINVAL_ARG -2
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#define QCOM_SCM_ERROR -1
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#define QCOM_SCM_INTERRUPTED 1
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#define QCOM_SCM_WAITQ_SLEEP 2
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static inline int qcom_scm_remap_error(int err)
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{
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