dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller
Add dedicated schema for the PCIe controllers found on X1E80100. Link: https://lore.kernel.org/linux-pci/20240301-x1e80100-pci-v4-1-7ab7e281d647@linaro.org Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Abel Vesa
Krzysztof Wilczyński
parent
bf79e33cdd
commit
692eadd516
165
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
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Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm X1E80100 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
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the Synopsys DesignWare PCIe IP.
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properties:
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compatible:
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const: qcom,pcie-x1e80100
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: noc_aggr # Aggre NoC PCIe AXI clock
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- const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
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interrupts:
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minItems: 8
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maxItems: 8
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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items:
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- const: pci # PCIe core reset
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- const: link_down # PCIe link down reset
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1c08000 {
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compatible = "qcom,pcie-x1e80100";
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reg = <0 0x01c08000 0 0x3000>,
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<0 0x7c000000 0 0xf1d>,
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<0 0x7c000f40 0 0xa8>,
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<0 0x7c001000 0 0x1000>,
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<0 0x7c100000 0 0x100000>,
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<0 0x01c0b000 0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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linux,pci-domain = <0>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
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<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_4_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
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<&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"noc_aggr",
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"cnoc_sf_axi";
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dma-coherent;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
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<0x100 &apps_smmu 0x1401 0x1>;
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phys = <&pcie4_phy>;
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phy-names = "pciephy";
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pinctrl-0 = <&pcie0_default_state>;
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pinctrl-names = "default";
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power-domains = <&gcc GCC_PCIE_4_GDSC>;
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resets = <&gcc GCC_PCIE_4_BCR>;
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reset-names = "pci";
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perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
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};
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};
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