kevin/linux
1
Fork 0
Code

MIPS: GIC: Generate redirect block accessors

Browse Source 
With CM 3.5 the "core-other" register block evolves into the "redirect"
register block, which is capable of accessing not only the core local
registers of other cores but also the shared/global registers of other
clusters.

This patch generates accessor functions for shared/global registers
accessed via the redirect block, with "redir_" inserted after "gic_" in
their names. For example the accessor function:

  read_gic_config()

...accesses the GIC_CONFIG register of the GIC in the local cluster.
With this patch a new function:

  read_gic_redir_config()

...is added which accesses the GIC_CONFIG register of the GIC in
whichever cluster the GCR_CL_REDIRECT register is configured to access.

This mirrors the similar redirect block accessors already provided for
the CM & CPC.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Paul Burton 2024-05-11 12:43:29 +02:00 committed by Thomas Bogendoerfer
parent 36675ac2a7
commit 680e7863de
1 changed files with 34 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
arch/mips/include/asm/mips-gic.h
View File

@ -28,11 +28,13 @@ extern void __iomem *mips_gic_base;
/* For read-only shared registers */
#define GIC_ACCESSOR_RO(sz, off, name) \
CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
/* For read-write shared registers */
#define GIC_ACCESSOR_RW(sz, off, name) \
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
/* For read-only local registers */
#define GIC_VX_ACCESSOR_RO(sz, off, name) \
@ -45,7 +47,7 @@ extern void __iomem *mips_gic_base;
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
/* For read-only shared per-interrupt registers */
#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
#define _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
static inline void __iomem *addr_gic_##name(unsigned int intr) \
{ \
return mips_gic_base + (off) + (intr * (stride)); \
@ -58,8 +60,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \
}
/* For read-write shared per-interrupt registers */
#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
#define _GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
\
static inline void write_gic_##name(unsigned int intr, \
unsigned int val) \
@ -68,22 +70,30 @@ static inline void write_gic_##name(unsigned int intr, \
__raw_writel(val, addr_gic_##name(intr)); \
}
#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name)
#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name)
/* For read-only local per-interrupt registers */
#define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
stride, vl_##name) \
GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
stride, vo_##name)
/* For read-write local per-interrupt registers */
#define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
stride, vl_##name) \
GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
stride, vo_##name)
/* For read-only shared bit-per-interrupt registers */
#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \
#define _GIC_ACCESSOR_RO_INTR_BIT(off, name) \
static inline void __iomem *addr_gic_##name(void) \
{ \
return mips_gic_base + (off); \
@ -106,8 +116,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \
}
/* For read-write shared bit-per-interrupt registers */
#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \
GIC_ACCESSOR_RO_INTR_BIT(off, name) \
#define _GIC_ACCESSOR_RW_INTR_BIT(off, name) \
_GIC_ACCESSOR_RO_INTR_BIT(off, name) \
\
static inline void write_gic_##name(unsigned int intr) \
{ \
@ -146,6 +156,14 @@ static inline void change_gic_##name(unsigned int intr, \
} \
}
#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \
_GIC_ACCESSOR_RO_INTR_BIT(off, name) \
_GIC_ACCESSOR_RO_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name)
#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \
_GIC_ACCESSOR_RW_INTR_BIT(off, name) \
_GIC_ACCESSOR_RW_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name)
/* For read-only local bit-per-interrupt registers */
#define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name) \
GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
@ -155,9 +173,9 @@ static inline void change_gic_##name(unsigned int intr, \
/* For read-write local bit-per-interrupt registers */
#define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name) \
GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
_GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
vl_##name) \
GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \
_GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \
vo_##name)
/* GIC_SH_CONFIG - Information about the GIC configuration */