i3c: dw: Add power management support
Add support for runtime and system power management. Handle clocks, resets, pads as part of suspend and resume. Restore controller registers that could be lost due to suspend. Finally add get and put calls appropriately in functions which access controller : bus_init, do_daa, send_ccc_cmd, priv_xfers, i2c_xfers, ibi and hot-join. Signed-off-by: Aniket <aniketmaurya@google.com> Link: https://lore.kernel.org/r/20240708062103.3296587-4-aniketmaurya@google.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Aniket
Alexandre Belloni
parent
effd21743c
commit
62fe9d06f5
@ -17,7 +17,9 @@
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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@ -217,7 +219,7 @@
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#define I3C_BUS_THIGH_MAX_NS 41
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#define XFER_TIMEOUT (msecs_to_jiffies(1000))
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#define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */
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struct dw_i3c_cmd {
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u32 cmd_lo;
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u32 cmd_hi;
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@ -650,29 +652,38 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
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struct i3c_device_info info = { };
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int ret;
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ret = pm_runtime_resume_and_get(master->dev);
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if (ret < 0) {
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dev_err(master->dev,
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"<%s> cannot resume i3c bus master, err: %d\n",
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__func__, ret);
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return ret;
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}
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ret = master->platform_ops->init(master);
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if (ret)
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return ret;
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goto rpm_out;
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switch (bus->mode) {
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case I3C_BUS_MODE_MIXED_FAST:
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case I3C_BUS_MODE_MIXED_LIMITED:
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ret = dw_i2c_clk_cfg(master);
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if (ret)
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return ret;
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goto rpm_out;
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fallthrough;
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case I3C_BUS_MODE_PURE:
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ret = dw_i3c_clk_cfg(master);
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if (ret)
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return ret;
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goto rpm_out;
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break;
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default:
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return -EINVAL;
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ret = -EINVAL;
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goto rpm_out;
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}
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ret = i3c_master_get_free_addr(m, 0);
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if (ret < 0)
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return ret;
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goto rpm_out;
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writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
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master->regs + DEVICE_ADDR);
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@ -682,12 +693,15 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
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ret = i3c_master_set_info(&master->base, &info);
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if (ret)
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return ret;
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goto rpm_out;
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dw_i3c_master_set_intr_regs(master);
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dw_i3c_master_enable(master);
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return 0;
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rpm_out:
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return ret;
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}
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static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
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@ -789,11 +803,21 @@ static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
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if (ccc->id == I3C_CCC_ENTDAA)
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return -EINVAL;
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ret = pm_runtime_resume_and_get(master->dev);
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if (ret < 0) {
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dev_err(master->dev,
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"<%s> cannot resume i3c bus master, err: %d\n",
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__func__, ret);
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return ret;
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}
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if (ccc->rnw)
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ret = dw_i3c_ccc_get(master, ccc);
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else
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ret = dw_i3c_ccc_set(master, ccc);
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return ret;
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}
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@ -806,6 +830,14 @@ static int dw_i3c_master_daa(struct i3c_master_controller *m)
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u8 p, last_addr = 0;
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int ret, pos;
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ret = pm_runtime_resume_and_get(master->dev);
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if (ret < 0) {
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dev_err(master->dev,
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"<%s> cannot resume i3c bus master, err: %d\n",
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__func__, ret);
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return ret;
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}
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olddevs = ~(master->free_pos);
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/* Prepare DAT before launching DAA. */
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@ -814,8 +846,10 @@ static int dw_i3c_master_daa(struct i3c_master_controller *m)
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continue;
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ret = i3c_master_get_free_addr(m, last_addr + 1);
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if (ret < 0)
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return -ENOSPC;
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if (ret < 0) {
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ret = -ENOSPC;
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goto rpm_out;
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}
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master->devs[pos].addr = ret;
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p = even_parity(ret);
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@ -825,16 +859,21 @@ static int dw_i3c_master_daa(struct i3c_master_controller *m)
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writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
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master->regs +
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DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
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ret = 0;
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}
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xfer = dw_i3c_master_alloc_xfer(master, 1);
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if (!xfer)
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return -ENOMEM;
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if (!xfer) {
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ret = -ENOMEM;
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goto rpm_out;
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}
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pos = dw_i3c_master_get_free_pos(master);
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if (pos < 0) {
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dw_i3c_master_free_xfer(xfer);
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return pos;
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ret = pos;
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goto rpm_out;
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}
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cmd = &xfer->cmds[0];
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cmd->cmd_hi = 0x1;
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@ -859,7 +898,10 @@ static int dw_i3c_master_daa(struct i3c_master_controller *m)
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dw_i3c_master_free_xfer(xfer);
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return 0;
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rpm_out:
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return ret;
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}
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static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
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@ -894,6 +936,14 @@ static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
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if (!xfer)
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return -ENOMEM;
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ret = pm_runtime_resume_and_get(master->dev);
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if (ret < 0) {
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dev_err(master->dev,
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"<%s> cannot resume i3c bus master, err: %d\n",
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__func__, ret);
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return ret;
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}
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for (i = 0; i < i3c_nxfers; i++) {
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struct dw_i3c_cmd *cmd = &xfer->cmds[i];
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@ -935,6 +985,8 @@ static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
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ret = xfer->ret;
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dw_i3c_master_free_xfer(xfer);
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return ret;
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}
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@ -1045,6 +1097,14 @@ static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
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if (!xfer)
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return -ENOMEM;
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ret = pm_runtime_resume_and_get(master->dev);
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if (ret < 0) {
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dev_err(master->dev,
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"<%s> cannot resume i3c bus master, err: %d\n",
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__func__, ret);
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return ret;
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}
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for (i = 0; i < i2c_nxfers; i++) {
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struct dw_i3c_cmd *cmd = &xfer->cmds[i];
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@ -1075,6 +1135,8 @@ static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
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ret = xfer->ret;
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dw_i3c_master_free_xfer(xfer);
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return ret;
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}
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@ -1217,6 +1279,15 @@ static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master,
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static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m)
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{
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struct dw_i3c_master *master = to_dw_i3c_master(m);
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int ret;
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ret = pm_runtime_resume_and_get(master->dev);
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if (ret < 0) {
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dev_err(master->dev,
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"<%s> cannot resume i3c bus master, err: %d\n",
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__func__, ret);
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return ret;
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}
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dw_i3c_master_enable_sir_signal(master, true);
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writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK,
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@ -1232,6 +1303,8 @@ static int dw_i3c_master_disable_hotjoin(struct i3c_master_controller *m)
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writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
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master->regs + DEVICE_CTRL);
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return 0;
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}
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@ -1242,12 +1315,23 @@ static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
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struct dw_i3c_master *master = to_dw_i3c_master(m);
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int rc;
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rc = pm_runtime_resume_and_get(master->dev);
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if (rc < 0) {
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dev_err(master->dev,
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"<%s> cannot resume i3c bus master, err: %d\n",
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__func__, rc);
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return rc;
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}
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dw_i3c_master_set_sir_enabled(master, dev, data->index, true);
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rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
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if (rc)
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if (rc) {
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dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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}
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return rc;
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}
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@ -1265,6 +1349,8 @@ static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
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dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return 0;
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}
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@ -1465,6 +1551,8 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
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if (!master->platform_ops)
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master->platform_ops = &dw_i3c_platform_ops_default;
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master->dev = &pdev->dev;
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master->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(master->regs))
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return PTR_ERR(master->regs);
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@ -1497,6 +1585,11 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
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platform_set_drvdata(pdev, master);
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pm_runtime_set_autosuspend_delay(&pdev->dev, RPM_AUTOSUSPEND_TIMEOUT);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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/* Information regarding the FIFOs/QUEUEs depth */
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ret = readl(master->regs + QUEUE_STATUS_LEVEL);
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master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
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@ -1513,10 +1606,15 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
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ret = i3c_master_register(&master->base, &pdev->dev,
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&dw_mipi_i3c_ops, false);
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if (ret)
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goto err_assert_rst;
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goto err_disable_pm;
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return 0;
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err_disable_pm:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_dont_use_autosuspend(&pdev->dev);
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err_assert_rst:
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reset_control_assert(master->core_rst);
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@ -1528,7 +1626,9 @@ void dw_i3c_common_remove(struct dw_i3c_master *master)
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{
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i3c_master_unregister(&master->base);
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reset_control_assert(master->core_rst);
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pm_runtime_disable(master->dev);
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pm_runtime_set_suspended(master->dev);
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pm_runtime_dont_use_autosuspend(master->dev);
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}
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EXPORT_SYMBOL_GPL(dw_i3c_common_remove);
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@ -1552,6 +1652,96 @@ static void dw_i3c_remove(struct platform_device *pdev)
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dw_i3c_common_remove(master);
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}
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static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master)
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{
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u32 pos, reg_val;
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writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr),
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master->regs + DEVICE_ADDR);
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for (pos = 0; pos < master->maxdevs; pos++) {
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if (master->free_pos & BIT(pos))
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continue;
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if (master->devs[pos].is_i2c_addr)
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reg_val = DEV_ADDR_TABLE_LEGACY_I2C_DEV |
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DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr);
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else
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reg_val = DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
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writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
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}
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}
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static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master)
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{
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writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
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writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING);
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writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
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writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING);
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if (master->i2c_slv_prsnt) {
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writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING);
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writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING);
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}
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}
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static int dw_i3c_master_enable_clks(struct dw_i3c_master *master)
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{
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int ret = 0;
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ret = clk_prepare_enable(master->core_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(master->pclk);
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if (ret) {
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clk_disable_unprepare(master->core_clk);
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return ret;
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}
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return 0;
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}
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static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master)
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{
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clk_disable_unprepare(master->pclk);
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clk_disable_unprepare(master->core_clk);
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}
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static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev)
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{
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struct dw_i3c_master *master = dev_get_drvdata(dev);
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dw_i3c_master_disable(master);
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reset_control_assert(master->core_rst);
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dw_i3c_master_disable_clks(master);
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pinctrl_pm_select_sleep_state(dev);
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return 0;
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}
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static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev)
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{
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struct dw_i3c_master *master = dev_get_drvdata(dev);
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pinctrl_pm_select_default_state(dev);
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dw_i3c_master_enable_clks(master);
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reset_control_deassert(master->core_rst);
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dw_i3c_master_set_intr_regs(master);
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dw_i3c_master_restore_timing_regs(master);
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dw_i3c_master_restore_addrs(master);
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dw_i3c_master_enable(master);
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return 0;
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}
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static const struct dev_pm_ops dw_i3c_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_resume, NULL)
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};
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static const struct of_device_id dw_i3c_master_of_match[] = {
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{ .compatible = "snps,dw-i3c-master-1.00a", },
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{},
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@ -1564,6 +1754,7 @@ static struct platform_driver dw_i3c_driver = {
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.driver = {
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.name = "dw-i3c-master",
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.of_match_table = dw_i3c_master_of_match,
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.pm = &dw_i3c_pm_ops,
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},
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};
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module_platform_driver(dw_i3c_driver);
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@ -25,6 +25,7 @@ struct dw_i3c_dat_entry {
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struct dw_i3c_master {
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||||
struct i3c_master_controller base;
|
||||
struct device *dev;
|
||||
u16 maxdevs;
|
||||
u16 datstartaddr;
|
||||
u32 free_pos;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user