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riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

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Before cacheinfo can be built correctly, we need to initialize level
and type. Since RISC-V currently does not have a register group that
describes cache-related attributes like ARM64, we cannot obtain them
directly, so now we obtain cache leaves from the ACPI PPTT table
(acpi_get_cache_info()) and set the cache type through split_levels.

Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Link: https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Yunhui Cui 2024-06-17 21:14:24 +08:00 committed by Palmer Dabbelt
parent ee3fab10cb
commit 604f32ea69
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1 changed files with 22 additions and 0 deletions
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22
arch/riscv/kernel/cacheinfo.c
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@ -3,6 +3,7 @@
* Copyright (C) 2017 SiFive
*/
#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <asm/cacheinfo.h>
@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
struct device_node *prev = NULL;
int levels = 1, level = 1;
if (!acpi_disabled) {
int ret, fw_levels, split_levels;
ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
if (ret)
return ret;
BUG_ON((split_levels > fw_levels) ||
(split_levels + fw_levels > this_cpu_ci->num_leaves));
for (; level <= this_cpu_ci->num_levels; level++) {
if (level <= split_levels) {
ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
} else {
ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
}
}
return 0;
}
if (of_property_read_bool(np, "cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
if (of_property_read_bool(np, "i-cache-size"))