Documentation: arm64: Update memory.rst for TBI
Most of memory.rst was written very early, at a time where TBI (Top Byte Ignore) was not enabled. Nowadays TBI0 is always enabled, and TBI1 may be enabled, depending on the kernel configuration. This means that VA bits 63:56 cannot generally be assumed to have any particular value. Regardless of TBI, TTBRx selection is done based on bit 55; update memory.rst accordingly. Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20240702091349.356008-1-kevin.brodsky@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -18,12 +18,10 @@ ARMv8.2 adds optional support for Large Virtual Address space. This is
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only available when running with a 64KB page size and expands the
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only available when running with a 64KB page size and expands the
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number of descriptors in the first level of translation.
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number of descriptors in the first level of translation.
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User addresses have bits 63:48 set to 0 while the kernel addresses have
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TTBRx selection is given by bit 55 of the virtual address. The
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the same bits set to 1. TTBRx selection is given by bit 63 of the
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swapper_pg_dir contains only kernel (global) mappings while the user pgd
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virtual address. The swapper_pg_dir contains only kernel (global)
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contains only user (non-global) mappings. The swapper_pg_dir address is
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mappings while the user pgd contains only user (non-global) mappings.
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written to TTBR1 and never written to TTBR0.
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The swapper_pg_dir address is written to TTBR1 and never written to
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TTBR0.
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AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
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AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
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@ -65,14 +63,14 @@ Translation table lookup with 4KB pages::
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+--------+--------+--------+--------+--------+--------+--------+--------+
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+--------+--------+--------+--------+--------+--------+--------+--------+
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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+--------+--------+--------+--------+--------+--------+--------+--------+
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+--------+--------+--------+--------+--------+--------+--------+--------+
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| | | | | |
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| | | | | v
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| | | | | v
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| | | | | [11:0] in-page offset
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| | | | | [11:0] in-page offset
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| | | | +-> [20:12] L3 index
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| | | | +-> [20:12] L3 index
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| | | +-----------> [29:21] L2 index
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| | | +-----------> [29:21] L2 index
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| | +---------------------> [38:30] L1 index
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| | +---------------------> [38:30] L1 index
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| +-------------------------------> [47:39] L0 index
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| +-------------------------------> [47:39] L0 index
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+-------------------------------------------------> [63] TTBR0/1
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+----------------------------------------> [55] TTBR0/1
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Translation table lookup with 64KB pages::
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Translation table lookup with 64KB pages::
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@ -80,14 +78,14 @@ Translation table lookup with 64KB pages::
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+--------+--------+--------+--------+--------+--------+--------+--------+
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+--------+--------+--------+--------+--------+--------+--------+--------+
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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+--------+--------+--------+--------+--------+--------+--------+--------+
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+--------+--------+--------+--------+--------+--------+--------+--------+
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| | | | v
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| | | | [15:0] in-page offset
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| | | | [15:0] in-page offset
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| | | +----------> [28:16] L3 index
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| | | +----------> [28:16] L3 index
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| | +--------------------------> [41:29] L2 index
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| | +--------------------------> [41:29] L2 index
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| +-------------------------------> [47:42] L1 index (48-bit)
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| +-------------------------------> [47:42] L1 index (48-bit)
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| [51:42] L1 index (52-bit)
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| [51:42] L1 index (52-bit)
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+-------------------------------------------------> [63] TTBR0/1
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+----------------------------------------> [55] TTBR0/1
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When using KVM without the Virtualization Host Extensions, the
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When using KVM without the Virtualization Host Extensions, the
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