drm/panthor: Add the GPU logical block
Handles everything that's not related to the FW, the MMU or the scheduler. This is the block dealing with the GPU property retrieval, the GPU block power on/off logic, and some global operations, like global cache flushing. v6: - Add Maxime's and Heiko's acks v5: - Fix GPU_MODEL() kernel doc - Fix test in panthor_gpu_block_power_off() - Add Steve's R-b v4: - Expose CORE_FEATURES through DEV_QUERY v3: - Add acks for the MIT/GPL2 relicensing - Use macros to extract GPU ID info - Make sure we reset clear pending_reqs bits when wait_event_timeout() times out but the corresponding bit is cleared in GPU_INT_RAWSTAT (can happen if the IRQ is masked or HW takes to long to call the IRQ handler) - GPU_MODEL now takes separate arch and product majors to be more readable. - Drop GPU_IRQ_MCU_STATUS_CHANGED from interrupt mask. - Handle GPU_IRQ_PROTM_FAULT correctly (don't output registers that are not updated for protected interrupts). - Minor code tidy ups Cc: Alexey Sheplyakov <asheplyakov@basealt.ru> # MIT+GPL2 relicensing Co-developed-by: Steven Price <steven.price@arm.com> Signed-off-by: Steven Price <steven.price@arm.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Steven Price <steven.price@arm.com> # MIT+GPL2 relicensing,Arm Acked-by: Grant Likely <grant.likely@linaro.org> # MIT+GPL2 relicensing,Linaro Acked-by: Boris Brezillon <boris.brezillon@collabora.com> # MIT+GPL2 relicensing,Collabora Reviewed-by: Steven Price <steven.price@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20240229162230.2634044-5-boris.brezillon@collabora.com
This commit is contained in:
Boris Brezillon
parent
5fe909cae1
commit
5cd894e258
482
drivers/gpu/drm/panthor/panthor_gpu.c
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482
drivers/gpu/drm/panthor/panthor_gpu.c
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@ -0,0 +1,482 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
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/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
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/* Copyright 2019 Collabora ltd. */
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#include <linux/bitfield.h>
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#include <linux/bitmap.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_managed.h>
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#include "panthor_device.h"
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#include "panthor_gpu.h"
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#include "panthor_regs.h"
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/**
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* struct panthor_gpu - GPU block management data.
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*/
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struct panthor_gpu {
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/** @irq: GPU irq. */
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struct panthor_irq irq;
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/** @reqs_lock: Lock protecting access to pending_reqs. */
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spinlock_t reqs_lock;
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/** @pending_reqs: Pending GPU requests. */
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u32 pending_reqs;
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/** @reqs_acked: GPU request wait queue. */
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wait_queue_head_t reqs_acked;
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};
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/**
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* struct panthor_model - GPU model description
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*/
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struct panthor_model {
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/** @name: Model name. */
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const char *name;
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/** @arch_major: Major version number of architecture. */
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u8 arch_major;
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/** @product_major: Major version number of product. */
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u8 product_major;
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};
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/**
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* GPU_MODEL() - Define a GPU model. A GPU product can be uniquely identified
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* by a combination of the major architecture version and the major product
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* version.
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* @_name: Name for the GPU model.
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* @_arch_major: Architecture major.
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* @_product_major: Product major.
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*/
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#define GPU_MODEL(_name, _arch_major, _product_major) \
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{\
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.name = __stringify(_name), \
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.arch_major = _arch_major, \
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.product_major = _product_major, \
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}
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static const struct panthor_model gpu_models[] = {
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GPU_MODEL(g610, 10, 7),
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{},
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};
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#define GPU_INTERRUPTS_MASK \
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(GPU_IRQ_FAULT | \
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GPU_IRQ_PROTM_FAULT | \
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GPU_IRQ_RESET_COMPLETED | \
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GPU_IRQ_CLEAN_CACHES_COMPLETED)
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static void panthor_gpu_init_info(struct panthor_device *ptdev)
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{
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const struct panthor_model *model;
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u32 arch_major, product_major;
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u32 major, minor, status;
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unsigned int i;
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ptdev->gpu_info.gpu_id = gpu_read(ptdev, GPU_ID);
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ptdev->gpu_info.csf_id = gpu_read(ptdev, GPU_CSF_ID);
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ptdev->gpu_info.gpu_rev = gpu_read(ptdev, GPU_REVID);
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ptdev->gpu_info.core_features = gpu_read(ptdev, GPU_CORE_FEATURES);
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ptdev->gpu_info.l2_features = gpu_read(ptdev, GPU_L2_FEATURES);
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ptdev->gpu_info.tiler_features = gpu_read(ptdev, GPU_TILER_FEATURES);
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ptdev->gpu_info.mem_features = gpu_read(ptdev, GPU_MEM_FEATURES);
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ptdev->gpu_info.mmu_features = gpu_read(ptdev, GPU_MMU_FEATURES);
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ptdev->gpu_info.thread_features = gpu_read(ptdev, GPU_THREAD_FEATURES);
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ptdev->gpu_info.max_threads = gpu_read(ptdev, GPU_THREAD_MAX_THREADS);
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ptdev->gpu_info.thread_max_workgroup_size = gpu_read(ptdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
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ptdev->gpu_info.thread_max_barrier_size = gpu_read(ptdev, GPU_THREAD_MAX_BARRIER_SIZE);
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ptdev->gpu_info.coherency_features = gpu_read(ptdev, GPU_COHERENCY_FEATURES);
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for (i = 0; i < 4; i++)
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ptdev->gpu_info.texture_features[i] = gpu_read(ptdev, GPU_TEXTURE_FEATURES(i));
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ptdev->gpu_info.as_present = gpu_read(ptdev, GPU_AS_PRESENT);
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ptdev->gpu_info.shader_present = gpu_read(ptdev, GPU_SHADER_PRESENT_LO);
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ptdev->gpu_info.shader_present |= (u64)gpu_read(ptdev, GPU_SHADER_PRESENT_HI) << 32;
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ptdev->gpu_info.tiler_present = gpu_read(ptdev, GPU_TILER_PRESENT_LO);
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ptdev->gpu_info.tiler_present |= (u64)gpu_read(ptdev, GPU_TILER_PRESENT_HI) << 32;
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ptdev->gpu_info.l2_present = gpu_read(ptdev, GPU_L2_PRESENT_LO);
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ptdev->gpu_info.l2_present |= (u64)gpu_read(ptdev, GPU_L2_PRESENT_HI) << 32;
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arch_major = GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id);
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product_major = GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id);
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major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id);
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minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id);
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status = GPU_VER_STATUS(ptdev->gpu_info.gpu_id);
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for (model = gpu_models; model->name; model++) {
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if (model->arch_major == arch_major &&
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model->product_major == product_major)
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break;
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}
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drm_info(&ptdev->base,
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"mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
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model->name ?: "unknown", ptdev->gpu_info.gpu_id >> 16,
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major, minor, status);
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drm_info(&ptdev->base,
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"Features: L2:%#x Tiler:%#x Mem:%#x MMU:%#x AS:%#x",
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ptdev->gpu_info.l2_features,
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ptdev->gpu_info.tiler_features,
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ptdev->gpu_info.mem_features,
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ptdev->gpu_info.mmu_features,
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ptdev->gpu_info.as_present);
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drm_info(&ptdev->base,
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"shader_present=0x%0llx l2_present=0x%0llx tiler_present=0x%0llx",
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ptdev->gpu_info.shader_present, ptdev->gpu_info.l2_present,
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ptdev->gpu_info.tiler_present);
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}
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static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status)
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{
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if (status & GPU_IRQ_FAULT) {
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u32 fault_status = gpu_read(ptdev, GPU_FAULT_STATUS);
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u64 address = ((u64)gpu_read(ptdev, GPU_FAULT_ADDR_HI) << 32) |
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gpu_read(ptdev, GPU_FAULT_ADDR_LO);
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drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
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fault_status, panthor_exception_name(ptdev, fault_status & 0xFF),
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address);
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}
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if (status & GPU_IRQ_PROTM_FAULT)
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drm_warn(&ptdev->base, "GPU Fault in protected mode\n");
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spin_lock(&ptdev->gpu->reqs_lock);
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if (status & ptdev->gpu->pending_reqs) {
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ptdev->gpu->pending_reqs &= ~status;
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wake_up_all(&ptdev->gpu->reqs_acked);
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}
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spin_unlock(&ptdev->gpu->reqs_lock);
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}
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PANTHOR_IRQ_HANDLER(gpu, GPU, panthor_gpu_irq_handler);
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/**
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* panthor_gpu_unplug() - Called when the GPU is unplugged.
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* @ptdev: Device to unplug.
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*/
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void panthor_gpu_unplug(struct panthor_device *ptdev)
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{
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unsigned long flags;
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/* Make sure the IRQ handler is not running after that point. */
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panthor_gpu_irq_suspend(&ptdev->gpu->irq);
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/* Wake-up all waiters. */
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spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
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ptdev->gpu->pending_reqs = 0;
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wake_up_all(&ptdev->gpu->reqs_acked);
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spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
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}
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/**
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* panthor_gpu_init() - Initialize the GPU block
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* @ptdev: Device.
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*
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* Return: 0 on success, a negative error code otherwise.
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*/
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int panthor_gpu_init(struct panthor_device *ptdev)
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{
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struct panthor_gpu *gpu;
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u32 pa_bits;
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int ret, irq;
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gpu = drmm_kzalloc(&ptdev->base, sizeof(*gpu), GFP_KERNEL);
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if (!gpu)
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return -ENOMEM;
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spin_lock_init(&gpu->reqs_lock);
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init_waitqueue_head(&gpu->reqs_acked);
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ptdev->gpu = gpu;
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panthor_gpu_init_info(ptdev);
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dma_set_max_seg_size(ptdev->base.dev, UINT_MAX);
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pa_bits = GPU_MMU_FEATURES_PA_BITS(ptdev->gpu_info.mmu_features);
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ret = dma_set_mask_and_coherent(ptdev->base.dev, DMA_BIT_MASK(pa_bits));
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if (ret)
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return ret;
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irq = platform_get_irq_byname(to_platform_device(ptdev->base.dev), "gpu");
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if (irq <= 0)
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return ret;
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ret = panthor_request_gpu_irq(ptdev, &ptdev->gpu->irq, irq, GPU_INTERRUPTS_MASK);
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if (ret)
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return ret;
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return 0;
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}
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/**
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* panthor_gpu_block_power_off() - Power-off a specific block of the GPU
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* @ptdev: Device.
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* @blk_name: Block name.
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* @pwroff_reg: Power-off register for this block.
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* @pwrtrans_reg: Power transition register for this block.
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* @mask: Sub-elements to power-off.
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* @timeout_us: Timeout in microseconds.
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*
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* Return: 0 on success, a negative error code otherwise.
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*/
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int panthor_gpu_block_power_off(struct panthor_device *ptdev,
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const char *blk_name,
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u32 pwroff_reg, u32 pwrtrans_reg,
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u64 mask, u32 timeout_us)
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{
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u32 val, i;
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int ret;
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for (i = 0; i < 2; i++) {
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u32 mask32 = mask >> (i * 32);
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if (!mask32)
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continue;
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ret = readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4),
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val, !(mask32 & val),
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100, timeout_us);
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if (ret) {
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drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition",
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blk_name, mask);
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return ret;
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}
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}
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if (mask & GENMASK(31, 0))
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gpu_write(ptdev, pwroff_reg, mask);
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if (mask >> 32)
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gpu_write(ptdev, pwroff_reg + 4, mask >> 32);
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for (i = 0; i < 2; i++) {
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u32 mask32 = mask >> (i * 32);
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if (!mask32)
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continue;
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ret = readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4),
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val, !(mask32 & val),
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100, timeout_us);
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if (ret) {
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drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition",
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blk_name, mask);
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return ret;
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}
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}
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return 0;
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}
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/**
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* panthor_gpu_block_power_on() - Power-on a specific block of the GPU
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* @ptdev: Device.
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* @blk_name: Block name.
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* @pwron_reg: Power-on register for this block.
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* @pwrtrans_reg: Power transition register for this block.
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* @rdy_reg: Power transition ready register.
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* @mask: Sub-elements to power-on.
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* @timeout_us: Timeout in microseconds.
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*
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* Return: 0 on success, a negative error code otherwise.
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*/
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int panthor_gpu_block_power_on(struct panthor_device *ptdev,
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const char *blk_name,
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u32 pwron_reg, u32 pwrtrans_reg,
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u32 rdy_reg, u64 mask, u32 timeout_us)
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{
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u32 val, i;
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int ret;
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for (i = 0; i < 2; i++) {
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u32 mask32 = mask >> (i * 32);
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if (!mask32)
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continue;
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ret = readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4),
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val, !(mask32 & val),
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100, timeout_us);
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if (ret) {
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drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition",
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blk_name, mask);
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return ret;
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}
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}
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if (mask & GENMASK(31, 0))
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gpu_write(ptdev, pwron_reg, mask);
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if (mask >> 32)
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gpu_write(ptdev, pwron_reg + 4, mask >> 32);
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for (i = 0; i < 2; i++) {
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u32 mask32 = mask >> (i * 32);
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if (!mask32)
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continue;
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ret = readl_relaxed_poll_timeout(ptdev->iomem + rdy_reg + (i * 4),
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val, (mask32 & val) == mask32,
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100, timeout_us);
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if (ret) {
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drm_err(&ptdev->base, "timeout waiting on %s:%llx readyness",
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blk_name, mask);
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return ret;
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}
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}
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return 0;
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}
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/**
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* panthor_gpu_l2_power_on() - Power-on the L2-cache
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* @ptdev: Device.
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*
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* Return: 0 on success, a negative error code otherwise.
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*/
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int panthor_gpu_l2_power_on(struct panthor_device *ptdev)
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{
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if (ptdev->gpu_info.l2_present != 1) {
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/*
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* Only support one core group now.
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* ~(l2_present - 1) unsets all bits in l2_present except
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* the bottom bit. (l2_present - 2) has all the bits in
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* the first core group set. AND them together to generate
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* a mask of cores in the first core group.
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*/
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u64 core_mask = ~(ptdev->gpu_info.l2_present - 1) &
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(ptdev->gpu_info.l2_present - 2);
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drm_info_once(&ptdev->base, "using only 1st core group (%lu cores from %lu)\n",
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hweight64(core_mask),
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hweight64(ptdev->gpu_info.shader_present));
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}
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return panthor_gpu_power_on(ptdev, L2, 1, 20000);
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}
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/**
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* panthor_gpu_flush_caches() - Flush caches
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* @ptdev: Device.
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* @l2: L2 flush type.
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* @lsc: LSC flush type.
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* @other: Other flush type.
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*
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* Return: 0 on success, a negative error code otherwise.
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*/
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int panthor_gpu_flush_caches(struct panthor_device *ptdev,
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u32 l2, u32 lsc, u32 other)
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{
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bool timedout = false;
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unsigned long flags;
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spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
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if (!drm_WARN_ON(&ptdev->base,
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ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) {
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ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED;
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gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
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}
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spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
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if (!wait_event_timeout(ptdev->gpu->reqs_acked,
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!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED),
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msecs_to_jiffies(100))) {
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spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
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if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
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!(gpu_read(ptdev, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
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timedout = true;
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else
|
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ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;
|
||||
spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
|
||||
}
|
||||
|
||||
if (timedout) {
|
||||
drm_err(&ptdev->base, "Flush caches timeout");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* panthor_gpu_soft_reset() - Issue a soft-reset
|
||||
* @ptdev: Device.
|
||||
*
|
||||
* Return: 0 on success, a negative error code otherwise.
|
||||
*/
|
||||
int panthor_gpu_soft_reset(struct panthor_device *ptdev)
|
||||
{
|
||||
bool timedout = false;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
|
||||
if (!drm_WARN_ON(&ptdev->base,
|
||||
ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) {
|
||||
ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED;
|
||||
gpu_write(ptdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
|
||||
gpu_write(ptdev, GPU_CMD, GPU_SOFT_RESET);
|
||||
}
|
||||
spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
|
||||
|
||||
if (!wait_event_timeout(ptdev->gpu->reqs_acked,
|
||||
!(ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED),
|
||||
msecs_to_jiffies(100))) {
|
||||
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
|
||||
if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 &&
|
||||
!(gpu_read(ptdev, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
|
||||
timedout = true;
|
||||
else
|
||||
ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED;
|
||||
spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
|
||||
}
|
||||
|
||||
if (timedout) {
|
||||
drm_err(&ptdev->base, "Soft reset timeout");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* panthor_gpu_suspend() - Suspend the GPU block.
|
||||
* @ptdev: Device.
|
||||
*
|
||||
* Suspend the GPU irq. This should be called last in the suspend procedure,
|
||||
* after all other blocks have been suspented.
|
||||
*/
|
||||
void panthor_gpu_suspend(struct panthor_device *ptdev)
|
||||
{
|
||||
/*
|
||||
* It may be preferable to simply power down the L2, but for now just
|
||||
* soft-reset which will leave the L2 powered down.
|
||||
*/
|
||||
panthor_gpu_soft_reset(ptdev);
|
||||
panthor_gpu_irq_suspend(&ptdev->gpu->irq);
|
||||
}
|
||||
|
||||
/**
|
||||
* panthor_gpu_resume() - Resume the GPU block.
|
||||
* @ptdev: Device.
|
||||
*
|
||||
* Resume the IRQ handler and power-on the L2-cache.
|
||||
* The FW takes care of powering the other blocks.
|
||||
*/
|
||||
void panthor_gpu_resume(struct panthor_device *ptdev)
|
||||
{
|
||||
panthor_gpu_irq_resume(&ptdev->gpu->irq, GPU_INTERRUPTS_MASK);
|
||||
panthor_gpu_l2_power_on(ptdev);
|
||||
}
|
||||
52
drivers/gpu/drm/panthor/panthor_gpu.h
Normal file
52
drivers/gpu/drm/panthor/panthor_gpu.h
Normal file
@ -0,0 +1,52 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 or MIT */
|
||||
/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
|
||||
/* Copyright 2019 Collabora ltd. */
|
||||
|
||||
#ifndef __PANTHOR_GPU_H__
|
||||
#define __PANTHOR_GPU_H__
|
||||
|
||||
struct panthor_device;
|
||||
|
||||
int panthor_gpu_init(struct panthor_device *ptdev);
|
||||
void panthor_gpu_unplug(struct panthor_device *ptdev);
|
||||
void panthor_gpu_suspend(struct panthor_device *ptdev);
|
||||
void panthor_gpu_resume(struct panthor_device *ptdev);
|
||||
|
||||
int panthor_gpu_block_power_on(struct panthor_device *ptdev,
|
||||
const char *blk_name,
|
||||
u32 pwron_reg, u32 pwrtrans_reg,
|
||||
u32 rdy_reg, u64 mask, u32 timeout_us);
|
||||
int panthor_gpu_block_power_off(struct panthor_device *ptdev,
|
||||
const char *blk_name,
|
||||
u32 pwroff_reg, u32 pwrtrans_reg,
|
||||
u64 mask, u32 timeout_us);
|
||||
|
||||
/**
|
||||
* panthor_gpu_power_on() - Power on the GPU block.
|
||||
*
|
||||
* Return: 0 on success, a negative error code otherwise.
|
||||
*/
|
||||
#define panthor_gpu_power_on(ptdev, type, mask, timeout_us) \
|
||||
panthor_gpu_block_power_on(ptdev, #type, \
|
||||
type ## _PWRON_LO, \
|
||||
type ## _PWRTRANS_LO, \
|
||||
type ## _READY_LO, \
|
||||
mask, timeout_us)
|
||||
|
||||
/**
|
||||
* panthor_gpu_power_off() - Power off the GPU block.
|
||||
*
|
||||
* Return: 0 on success, a negative error code otherwise.
|
||||
*/
|
||||
#define panthor_gpu_power_off(ptdev, type, mask, timeout_us) \
|
||||
panthor_gpu_block_power_off(ptdev, #type, \
|
||||
type ## _PWROFF_LO, \
|
||||
type ## _PWRTRANS_LO, \
|
||||
mask, timeout_us)
|
||||
|
||||
int panthor_gpu_l2_power_on(struct panthor_device *ptdev);
|
||||
int panthor_gpu_flush_caches(struct panthor_device *ptdev,
|
||||
u32 l2, u32 lsc, u32 other);
|
||||
int panthor_gpu_soft_reset(struct panthor_device *ptdev);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user