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remoteproc: mediatek: Enable cache for mt8186 SCP

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This patch is for enabling cache in SCP. There is not enough space
on the SRAM of SCP. We need to run programs in DRAM. The DRAM power
and latency is much larger than SRAM, so cache is used to mitigate
the negative effects for performance. We set SCP registers for cache
size before loading SCP FW. (8KB+8KB) and also adjust ipi_buf_offset
in SRAM from 0x7bdb0 to 0x3bdb0 for enabling cache.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Tested-by: TingHan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220701121229.22756-2-allen-kh.cheng@mediatek.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
Allen-KH Cheng 2022-07-01 20:12:29 +08:00 committed by Mathieu Poirier
parent 50d6281ce9
commit 54439d20c0
1 changed files with 9 additions and 1 deletions
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10
drivers/remoteproc/mtk_scp.c
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@ -401,6 +401,14 @@ static int mt8186_scp_before_load(struct mtk_scp *scp)
writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
/*
* Set I-cache and D-cache size before loading SCP FW.
* SCP SRAM logical address may change when cache size setting differs.
*/
writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
scp->reg_base + MT8183_SCP_CACHE_CON);
writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
return 0;
}
@ -943,7 +951,7 @@ static const struct mtk_scp_of_data mt8186_of_data = {
.scp_da_to_va = mt8183_scp_da_to_va,
.host_to_scp_reg = MT8183_HOST_TO_SCP,
.host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT,
.ipi_buf_offset = 0x7bdb0,
.ipi_buf_offset = 0x3bdb0,
};
static const struct mtk_scp_of_data mt8192_of_data = {