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A handful of Qualcomm clk driver fixes:

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- Correct flags for X Elite USB MP GDSC and pcie pipediv2 clocks
  - Fix alpha PLL post_div mask for the cases where width is not
    specified
  - Avoid hangs in the SM8350 video driver (venus) by setting HW_CTRL
    trigger feature on the video clocks
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A handful of Qualcomm clk driver fixes:

   - Correct flags for X Elite USB MP GDSC and pcie pipediv2 clocks

   - Fix alpha PLL post_div mask for the cases where width is not
     specified

   - Avoid hangs in the SM8350 video driver (venus) by setting HW_CTRL
     trigger feature on the video clocks"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags
  clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks
  clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set
  clk: qcom: videocc-sm8350: use HW_CTRL_TRIGGER for vcodec GDSCs
This commit is contained in:
Linus Torvalds 2024-11-10 14:16:28 -08:00
commit 541f3d87b6
3 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -40,7 +40,7 @@
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
# define PLL_POST_DIV_SHIFT 8 # define PLL_POST_DIV_SHIFT 8
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
# define PLL_ALPHA_MSB BIT(15) # define PLL_ALPHA_MSB BIT(15)
# define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_EN BIT(24)
# define PLL_ALPHA_MODE BIT(25) # define PLL_ALPHA_MODE BIT(25)

12
drivers/clk/qcom/gcc-x1e80100.c
View File

@ -3123,7 +3123,7 @@ static struct clk_branch gcc_pcie_3_pipe_clk = {
static struct clk_branch gcc_pcie_3_pipediv2_clk = { static struct clk_branch gcc_pcie_3_pipediv2_clk = {
.halt_reg = 0x58060, .halt_reg = 0x58060,
.halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52020, .enable_reg = 0x52020,
.enable_mask = BIT(5), .enable_mask = BIT(5),
@ -3248,7 +3248,7 @@ static struct clk_branch gcc_pcie_4_pipe_clk = {
static struct clk_branch gcc_pcie_4_pipediv2_clk = { static struct clk_branch gcc_pcie_4_pipediv2_clk = {
.halt_reg = 0x6b054, .halt_reg = 0x6b054,
.halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52010, .enable_reg = 0x52010,
.enable_mask = BIT(27), .enable_mask = BIT(27),
@ -3373,7 +3373,7 @@ static struct clk_branch gcc_pcie_5_pipe_clk = {
static struct clk_branch gcc_pcie_5_pipediv2_clk = { static struct clk_branch gcc_pcie_5_pipediv2_clk = {
.halt_reg = 0x2f054, .halt_reg = 0x2f054,
.halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52018, .enable_reg = 0x52018,
.enable_mask = BIT(19), .enable_mask = BIT(19),
@ -3511,7 +3511,7 @@ static struct clk_branch gcc_pcie_6a_pipe_clk = {
static struct clk_branch gcc_pcie_6a_pipediv2_clk = { static struct clk_branch gcc_pcie_6a_pipediv2_clk = {
.halt_reg = 0x31060, .halt_reg = 0x31060,
.halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52018, .enable_reg = 0x52018,
.enable_mask = BIT(28), .enable_mask = BIT(28),
@ -3649,7 +3649,7 @@ static struct clk_branch gcc_pcie_6b_pipe_clk = {
static struct clk_branch gcc_pcie_6b_pipediv2_clk = { static struct clk_branch gcc_pcie_6b_pipediv2_clk = {
.halt_reg = 0x8d060, .halt_reg = 0x8d060,
.halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52010, .enable_reg = 0x52010,
.enable_mask = BIT(28), .enable_mask = BIT(28),
@ -6155,7 +6155,7 @@ static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
.pd = { .pd = {
.name = "gcc_usb3_mp_ss1_phy_gdsc", .name = "gcc_usb3_mp_ss1_phy_gdsc",
}, },
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_RET_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
}; };

4
drivers/clk/qcom/videocc-sm8350.c
View File

@ -452,7 +452,7 @@ static struct gdsc mvs0_gdsc = {
.pd = { .pd = {
.name = "mvs0_gdsc", .name = "mvs0_gdsc",
}, },
.flags = HW_CTRL | RETAIN_FF_ENABLE, .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE,
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
}; };
@ -461,7 +461,7 @@ static struct gdsc mvs1_gdsc = {
.pd = { .pd = {
.name = "mvs1_gdsc", .name = "mvs1_gdsc",
}, },
.flags = HW_CTRL | RETAIN_FF_ENABLE, .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE,
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
}; };