mailbox: imx-mailbox: support i.MX8ULP MU
i.MX8ULP MU has different register layout and bit layout compared with i.MX6SX/7ULP/8. So add enum imx_mu_type to show it is IMX_MU_V2 or IMX_MU_V1. For IMX_MU_V2 mu hardware, check it when calculating bit offset to get the correct offset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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@ -15,20 +15,6 @@
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
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#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
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#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
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#define IMX_MU_xSR_BRDIP BIT(9)
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
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/* Receive Interrupt Enable */
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#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
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/* Transmit Interrupt Enable */
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#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
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/* General Purpose Interrupt Request */
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#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
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#define IMX_MU_CHANS 16
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/* TX0/RX0/RXDB[0-3] */
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#define IMX_MU_SCU_CHANS 6
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@ -42,7 +28,7 @@ enum imx_mu_chan_type {
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};
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enum imx_mu_xcr {
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IMX_MU_CR,
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IMX_MU_GIER,
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IMX_MU_GCR,
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IMX_MU_TCR,
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IMX_MU_RCR,
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@ -87,16 +73,36 @@ struct imx_mu_priv {
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bool side_b;
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};
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enum imx_mu_type {
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IMX_MU_V1,
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IMX_MU_V2,
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};
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struct imx_mu_dcfg {
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
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int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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void (*init)(struct imx_mu_priv *priv);
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enum imx_mu_type type;
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u32 xTR; /* Transmit Register0 */
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u32 xRR; /* Receive Register0 */
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u32 xSR[4]; /* Status Registers */
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u32 xCR[4]; /* Control Registers */
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};
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#define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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#define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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/* Receive Interrupt Enable */
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#define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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/* Transmit Interrupt Enable */
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#define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Request */
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#define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct imx_mu_priv, mbox);
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@ -136,10 +142,10 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
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break;
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case IMX_MU_TYPE_TXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(cp->idx), 0);
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imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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@ -191,7 +197,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
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for (; i < msg->hdr.size; i++) {
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
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xsr,
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xsr & IMX_MU_xSR_TEn(i % 4),
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xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4),
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0, 100);
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if (ret) {
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dev_err(priv->dev, "Send data index: %d timeout\n", i);
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@ -200,7 +206,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
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imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
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}
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
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@ -218,7 +224,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
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int i, ret;
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u32 xsr;
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(0));
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
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*data++ = imx_mu_read(priv, priv->dcfg->xRR);
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if (msg.hdr.size > sizeof(msg) / 4) {
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@ -228,7 +234,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
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for (i = 1; i < msg.hdr.size; i++) {
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
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xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
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xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);
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if (ret) {
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dev_err(priv->dev, "timeout read idx %d\n", i);
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return ret;
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@ -236,7 +242,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
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*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
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}
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(0), 0);
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
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mbox_chan_received_data(cp->chan, (void *)&msg);
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return 0;
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@ -260,20 +266,20 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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case IMX_MU_TYPE_TX:
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ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
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val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
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val &= IMX_MU_xSR_TEn(cp->idx) &
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(ctrl & IMX_MU_xCR_TIEn(cp->idx));
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val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
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(ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
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break;
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case IMX_MU_TYPE_RX:
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ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
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val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
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val &= IMX_MU_xSR_RFn(cp->idx) &
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(ctrl & IMX_MU_xCR_RIEn(cp->idx));
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val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
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(ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
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break;
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case IMX_MU_TYPE_RXDB:
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ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
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ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
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val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
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val &= IMX_MU_xSR_GIPn(cp->idx) &
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(ctrl & IMX_MU_xCR_GIEn(cp->idx));
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val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
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(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
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break;
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default:
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break;
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@ -282,13 +288,17 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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if (!val)
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return IRQ_NONE;
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if (val == IMX_MU_xSR_TEn(cp->idx)) {
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
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if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
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(cp->type == IMX_MU_TYPE_TX)) {
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
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mbox_chan_txdone(chan, 0);
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} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
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} else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
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(cp->type == IMX_MU_TYPE_RX)) {
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priv->dcfg->rx(priv, cp);
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} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
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} else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
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(cp->type == IMX_MU_TYPE_RXDB)) {
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imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
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priv->dcfg->xSR[IMX_MU_GSR]);
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mbox_chan_received_data(chan, NULL);
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} else {
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dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
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@ -335,10 +345,10 @@ static int imx_mu_startup(struct mbox_chan *chan)
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switch (cp->type) {
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case IMX_MU_TYPE_RX:
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(cp->idx), 0);
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
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break;
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case IMX_MU_TYPE_RXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(cp->idx), 0);
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imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
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break;
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default:
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break;
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@ -360,13 +370,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
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break;
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case IMX_MU_TYPE_RX:
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(cp->idx));
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
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break;
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case IMX_MU_TYPE_RXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(cp->idx));
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imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
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break;
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default:
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break;
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@ -600,12 +610,23 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.xCR = {0x64, 0x64, 0x64, 0x64},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
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.tx = imx_mu_generic_tx,
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.rx = imx_mu_generic_rx,
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.init = imx_mu_init_generic,
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.type = IMX_MU_V2,
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.xTR = 0x200,
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.xRR = 0x280,
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.xSR = {0xC, 0x118, 0x124, 0x12C},
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.xCR = {0x110, 0x114, 0x120, 0x128},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
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.tx = imx_mu_scu_tx,
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.rx = imx_mu_scu_rx,
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.init = imx_mu_init_scu,
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.xTR = 0x0
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.xRR = 0x10
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.xTR = 0x0,
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.xRR = 0x10,
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.xSR = {0x20, 0x20, 0x20, 0x20},
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.xCR = {0x24, 0x24, 0x24, 0x24},
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};
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@ -613,6 +634,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
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static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
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{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
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{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
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{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
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{ },
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};
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