ASoC: loongson: Factor out loongson i2s enable clock functions
There are a few i2s clock enable operations in loongson_i2s_set_fmt(), convert them to simple helper functions called loongson_i2s_enable_mclk() and loongson_i2s_enable_bclk(). Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://patch.msgid.link/d6f6c818b0ecee87277f704b6a801cbbf5e712ce.1725844530.git.zhoubinbin@loongson.cn Signed-off-by: Mark Brown <broonie@kernel.org>
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ddb538a300
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@ -24,6 +24,9 @@
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#define LOONGSON_I2S_TX_ENABLE (I2S_CTRL_TX_EN | I2S_CTRL_TX_DMA_EN)
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#define LOONGSON_I2S_RX_ENABLE (I2S_CTRL_RX_EN | I2S_CTRL_RX_DMA_EN)
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#define LOONGSON_I2S_DEF_DELAY 10
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#define LOONGSON_I2S_DEF_TIMEOUT 500000
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static int loongson_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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@ -119,10 +122,40 @@ static int loongson_i2s_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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return 0;
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}
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static int loongson_i2s_enable_mclk(struct loongson_i2s *i2s)
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{
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u32 val;
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if (i2s->rev_id == 0)
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return 0;
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regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
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I2S_CTRL_MCLK_EN, I2S_CTRL_MCLK_EN);
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return regmap_read_poll_timeout_atomic(i2s->regmap,
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LS_I2S_CTRL, val,
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val & I2S_CTRL_MCLK_READY,
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LOONGSON_I2S_DEF_DELAY,
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LOONGSON_I2S_DEF_TIMEOUT);
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}
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static int loongson_i2s_enable_bclk(struct loongson_i2s *i2s)
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{
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u32 val;
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if (i2s->rev_id == 0)
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return 0;
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return regmap_read_poll_timeout_atomic(i2s->regmap,
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LS_I2S_CTRL, val,
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val & I2S_CTRL_CLK_READY,
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LOONGSON_I2S_DEF_DELAY,
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LOONGSON_I2S_DEF_TIMEOUT);
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}
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static int loongson_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct loongson_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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u32 val;
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int ret;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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@ -144,54 +177,29 @@ static int loongson_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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/* Enable master mode */
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regmap_update_bits(i2s->regmap, LS_I2S_CTRL, I2S_CTRL_MASTER,
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I2S_CTRL_MASTER);
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if (i2s->rev_id == 1) {
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ret = regmap_read_poll_timeout_atomic(i2s->regmap,
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LS_I2S_CTRL, val,
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val & I2S_CTRL_CLK_READY,
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10, 500000);
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if (ret < 0)
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dev_warn(dai->dev, "wait BCLK ready timeout\n");
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}
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ret = loongson_i2s_enable_bclk(i2s);
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if (ret < 0)
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dev_warn(dai->dev, "wait BCLK ready timeout\n");
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break;
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case SND_SOC_DAIFMT_BC_FP:
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/* Enable MCLK */
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if (i2s->rev_id == 1) {
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regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
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I2S_CTRL_MCLK_EN,
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I2S_CTRL_MCLK_EN);
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ret = regmap_read_poll_timeout_atomic(i2s->regmap,
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LS_I2S_CTRL, val,
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val & I2S_CTRL_MCLK_READY,
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10, 500000);
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if (ret < 0)
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dev_warn(dai->dev, "wait MCLK ready timeout\n");
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}
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ret = loongson_i2s_enable_mclk(i2s);
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if (ret < 0)
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dev_warn(dai->dev, "wait MCLK ready timeout\n");
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break;
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case SND_SOC_DAIFMT_BP_FP:
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/* Enable MCLK */
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if (i2s->rev_id == 1) {
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regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
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I2S_CTRL_MCLK_EN,
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I2S_CTRL_MCLK_EN);
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ret = regmap_read_poll_timeout_atomic(i2s->regmap,
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LS_I2S_CTRL, val,
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val & I2S_CTRL_MCLK_READY,
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10, 500000);
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if (ret < 0)
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dev_warn(dai->dev, "wait MCLK ready timeout\n");
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}
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ret = loongson_i2s_enable_mclk(i2s);
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if (ret < 0)
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dev_warn(dai->dev, "wait MCLK ready timeout\n");
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/* Enable master mode */
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regmap_update_bits(i2s->regmap, LS_I2S_CTRL, I2S_CTRL_MASTER,
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I2S_CTRL_MASTER);
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if (i2s->rev_id == 1) {
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ret = regmap_read_poll_timeout_atomic(i2s->regmap,
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LS_I2S_CTRL, val,
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val & I2S_CTRL_CLK_READY,
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10, 500000);
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if (ret < 0)
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dev_warn(dai->dev, "wait BCLK ready timeout\n");
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}
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ret = loongson_i2s_enable_bclk(i2s);
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if (ret < 0)
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dev_warn(dai->dev, "wait BCLK ready timeout\n");
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break;
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default:
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return -EINVAL;
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