Updates for clocksource/clockevent drivers:
- Remove the OXNAS driver instead of adding a new one! - A set of boring fixes, cleanups and improvements -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmT1ixwTHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoaIAEACUw02RVWQEbsmJCcnyTPAOoP99xphv IPH32UL9Iuq2rgsGOfTGDw8be2bnlUw8d2FEsUtR0lnwfsBDzQKxh+iHWUPzhosX VbhcN/tHC0KXzWL/dKPiCjS2CVRMlSRu39XN2+9typmf0GpK1IQzDHjKj5Z95Vdp Zb1tPm9N18ZSdT04dNRdNlkmdCjjMaPE9h0hpyIqALQD2TmTs9CwO7nxbf7hXJTB 4tLGOW1MznuIAhwLK0toSHmMKv8YTNn9arwDZ6PDDFpff06Q+Gw5YitsgzTFNNIh TlLQdq04DOiXOh47VwiU0Ixc/JdlxN0pxscfYN0KP6Odjs+IkE+cSyhfYNFQTaFc qN4C4j0FpCkFmsIeLpCg9FAU0eqA/ViRR1NR+TIJW9jRYMaJOBD3s9Kehv1Xj5di hOCh0EvU/TFZ2v1ZgSD3RWgIcvGnijKxvw1Rrh+ZTJTX2LnkXRJqQY9PTKfIFNLM LJoo/oXp6aAcpnrxIMvG2splxRihqpuzUpY+Y0SnOQnbgbPeZ3/lx7PMiXrfDIr7 y8npY/2upKLjC5TlbCX42FBTulQfeLWT8TI6yGwPOQudigdyeBDWNV3+lpLMxrJe s/MbARoOM9Nx2toz9qFa+yuKTcJtaSQfwmcwP1jQRei8O+MXkDe7HmfRnp0bMPF3 a5A0B/fdRjEEwQ== =dGVZ -----END PGP SIGNATURE----- Merge tag 'timers-core-2023-09-04-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull clocksource/clockevent driver updates from Thomas Gleixner: - Remove the OXNAS driver instead of adding a new one! - A set of boring fixes, cleanups and improvements * tag 'timers-core-2023-09-04-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource: Explicitly include correct DT includes clocksource/drivers/sun5i: Convert to platform device driver clocksource/drivers/sun5i: Remove pointless struct clocksource/drivers/sun5i: Remove duplication of code and data clocksource/drivers/loongson1: Set variable ls1x_timer_lock storage-class-specifier to static clocksource/drivers/arm_arch_timer: Disable timer before programming CVAL dt-bindings: timer: oxsemi,rps-timer: remove obsolete bindings clocksource/drivers/timer-oxnas-rps: Remove obsolete timer driver
This commit is contained in:
Linus Torvalds
commit
4accdb9895
@ -1,17 +0,0 @@
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Oxford Semiconductor OXNAS SoCs Family RPS Timer
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================================================
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Required properties:
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- compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer"
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- reg : Specifies base physical address and size of the registers.
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- interrupts : The interrupts of the two timers
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- clocks : The phandle of the timer clock source
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example:
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timer0: timer@200 {
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compatible = "oxsemi,ox810se-rps-timer";
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reg = <0x200 0x40>;
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clocks = <&rpsclk>;
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interrupts = <4 5>;
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};
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@ -461,13 +461,6 @@ config VF_PIT_TIMER
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help
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Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs.
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config OXNAS_RPS_TIMER
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bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST
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select TIMER_OF
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select CLKSRC_MMIO
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help
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This enables support for the Oxford Semiconductor OXNAS RPS timers.
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config SYS_SUPPORTS_SH_CMT
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bool
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@ -54,7 +54,6 @@ obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
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obj-$(CONFIG_MTK_CPUX_TIMER) += timer-mediatek-cpux.o
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obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o
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obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
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obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
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obj-$(CONFIG_OWL_TIMER) += timer-owl.o
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obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
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obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
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@ -792,6 +792,13 @@ static __always_inline void set_next_event_mem(const int access, unsigned long e
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u64 cnt;
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
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/* Timer must be disabled before programming CVAL */
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if (ctrl & ARCH_TIMER_CTRL_ENABLE) {
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
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}
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ctrl |= ARCH_TIMER_CTRL_ENABLE;
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ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
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@ -28,7 +28,7 @@
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#define CNTR_WIDTH 24
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DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
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static DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
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struct ls1x_clocksource {
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void __iomem *reg_base;
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@ -1,288 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* drivers/clocksource/timer-oxnas-rps.c
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*
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* Copyright (C) 2009 Oxford Semiconductor Ltd
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* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/clockchips.h>
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#include <linux/sched_clock.h>
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/* TIMER1 used as tick
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* TIMER2 used as clocksource
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*/
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/* Registers definitions */
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#define TIMER_LOAD_REG 0x0
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#define TIMER_CURR_REG 0x4
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#define TIMER_CTRL_REG 0x8
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#define TIMER_CLRINT_REG 0xC
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#define TIMER_BITS 24
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#define TIMER_MAX_VAL (BIT(TIMER_BITS) - 1)
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#define TIMER_PERIODIC BIT(6)
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#define TIMER_ENABLE BIT(7)
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#define TIMER_DIV1 (0)
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#define TIMER_DIV16 (1 << 2)
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#define TIMER_DIV256 (2 << 2)
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#define TIMER1_REG_OFFSET 0
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#define TIMER2_REG_OFFSET 0x20
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/* Clockevent & Clocksource data */
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struct oxnas_rps_timer {
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struct clock_event_device clkevent;
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void __iomem *clksrc_base;
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void __iomem *clkevt_base;
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unsigned long timer_period;
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unsigned int timer_prescaler;
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struct clk *clk;
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int irq;
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};
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static irqreturn_t oxnas_rps_timer_irq(int irq, void *dev_id)
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{
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struct oxnas_rps_timer *rps = dev_id;
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writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
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rps->clkevent.event_handler(&rps->clkevent);
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return IRQ_HANDLED;
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}
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static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps,
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unsigned long period,
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unsigned int periodic)
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{
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uint32_t cfg = rps->timer_prescaler;
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if (period)
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cfg |= TIMER_ENABLE;
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if (periodic)
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cfg |= TIMER_PERIODIC;
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writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG);
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writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG);
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}
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static int oxnas_rps_timer_shutdown(struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, 0, 0);
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return 0;
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}
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static int oxnas_rps_timer_set_periodic(struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, rps->timer_period, 1);
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return 0;
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}
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static int oxnas_rps_timer_set_oneshot(struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, rps->timer_period, 0);
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return 0;
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}
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static int oxnas_rps_timer_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, delta, 0);
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return 0;
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}
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static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps)
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{
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ulong clk_rate = clk_get_rate(rps->clk);
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ulong timer_rate;
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/* Start with prescaler 1 */
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rps->timer_prescaler = TIMER_DIV1;
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rps->timer_period = DIV_ROUND_UP(clk_rate, HZ);
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timer_rate = clk_rate;
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if (rps->timer_period > TIMER_MAX_VAL) {
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rps->timer_prescaler = TIMER_DIV16;
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timer_rate = clk_rate / 16;
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rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
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}
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if (rps->timer_period > TIMER_MAX_VAL) {
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rps->timer_prescaler = TIMER_DIV256;
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timer_rate = clk_rate / 256;
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rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
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}
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rps->clkevent.name = "oxnas-rps";
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rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ;
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rps->clkevent.tick_resume = oxnas_rps_timer_shutdown;
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rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown;
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rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic;
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rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot;
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rps->clkevent.set_next_event = oxnas_rps_timer_next_event;
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rps->clkevent.rating = 200;
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rps->clkevent.cpumask = cpu_possible_mask;
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rps->clkevent.irq = rps->irq;
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clockevents_config_and_register(&rps->clkevent,
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timer_rate,
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1,
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TIMER_MAX_VAL);
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pr_info("Registered clock event rate %luHz prescaler %x period %lu\n",
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clk_rate,
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rps->timer_prescaler,
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rps->timer_period);
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return 0;
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}
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/* Clocksource */
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static void __iomem *timer_sched_base;
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static u64 notrace oxnas_rps_read_sched_clock(void)
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{
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return ~readl_relaxed(timer_sched_base);
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}
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static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps)
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{
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ulong clk_rate = clk_get_rate(rps->clk);
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int ret;
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/* use prescale 16 */
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clk_rate = clk_rate / 16;
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writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG);
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writel_relaxed(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
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rps->clksrc_base + TIMER_CTRL_REG);
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timer_sched_base = rps->clksrc_base + TIMER_CURR_REG;
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sched_clock_register(oxnas_rps_read_sched_clock,
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TIMER_BITS, clk_rate);
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ret = clocksource_mmio_init(timer_sched_base,
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"oxnas_rps_clocksource_timer",
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clk_rate, 250, TIMER_BITS,
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clocksource_mmio_readl_down);
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if (WARN_ON(ret)) {
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pr_err("can't register clocksource\n");
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return ret;
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}
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pr_info("Registered clocksource rate %luHz\n", clk_rate);
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return 0;
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}
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static int __init oxnas_rps_timer_init(struct device_node *np)
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{
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struct oxnas_rps_timer *rps;
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void __iomem *base;
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int ret;
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rps = kzalloc(sizeof(*rps), GFP_KERNEL);
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if (!rps)
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return -ENOMEM;
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rps->clk = of_clk_get(np, 0);
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if (IS_ERR(rps->clk)) {
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ret = PTR_ERR(rps->clk);
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goto err_alloc;
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}
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ret = clk_prepare_enable(rps->clk);
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if (ret)
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goto err_clk;
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base = of_iomap(np, 0);
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if (!base) {
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ret = -ENXIO;
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goto err_clk_prepare;
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}
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rps->irq = irq_of_parse_and_map(np, 0);
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if (!rps->irq) {
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ret = -EINVAL;
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goto err_iomap;
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}
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rps->clkevt_base = base + TIMER1_REG_OFFSET;
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rps->clksrc_base = base + TIMER2_REG_OFFSET;
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/* Disable timers */
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writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG);
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writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG);
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writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG);
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writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG);
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writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
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writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG);
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ret = request_irq(rps->irq, oxnas_rps_timer_irq,
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IRQF_TIMER | IRQF_IRQPOLL,
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"rps-timer", rps);
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if (ret)
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goto err_iomap;
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ret = oxnas_rps_clocksource_init(rps);
|
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if (ret)
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goto err_irqreq;
|
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|
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ret = oxnas_rps_clockevent_init(rps);
|
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if (ret)
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goto err_irqreq;
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|
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return 0;
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|
||||
err_irqreq:
|
||||
free_irq(rps->irq, rps);
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||||
err_iomap:
|
||||
iounmap(base);
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||||
err_clk_prepare:
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||||
clk_disable_unprepare(rps->clk);
|
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err_clk:
|
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clk_put(rps->clk);
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err_alloc:
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kfree(rps);
|
||||
|
||||
return ret;
|
||||
}
|
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|
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TIMER_OF_DECLARE(ox810se_rps,
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"oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
|
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TIMER_OF_DECLARE(ox820_rps,
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"oxsemi,ox820-rps-timer", oxnas_rps_timer_init);
|
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@ -16,9 +16,7 @@
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#include <linux/irqreturn.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define TIMER_IRQ_EN_REG 0x00
|
||||
#define TIMER_IRQ_EN(val) BIT(val)
|
||||
@ -40,26 +38,16 @@ struct sun5i_timer {
|
||||
struct clk *clk;
|
||||
struct notifier_block clk_rate_cb;
|
||||
u32 ticks_per_jiffy;
|
||||
};
|
||||
|
||||
#define to_sun5i_timer(x) \
|
||||
container_of(x, struct sun5i_timer, clk_rate_cb)
|
||||
|
||||
struct sun5i_timer_clksrc {
|
||||
struct sun5i_timer timer;
|
||||
struct clocksource clksrc;
|
||||
};
|
||||
|
||||
#define to_sun5i_timer_clksrc(x) \
|
||||
container_of(x, struct sun5i_timer_clksrc, clksrc)
|
||||
|
||||
struct sun5i_timer_clkevt {
|
||||
struct sun5i_timer timer;
|
||||
struct clock_event_device clkevt;
|
||||
};
|
||||
|
||||
#define to_sun5i_timer_clkevt(x) \
|
||||
container_of(x, struct sun5i_timer_clkevt, clkevt)
|
||||
#define nb_to_sun5i_timer(x) \
|
||||
container_of(x, struct sun5i_timer, clk_rate_cb)
|
||||
#define clksrc_to_sun5i_timer(x) \
|
||||
container_of(x, struct sun5i_timer, clksrc)
|
||||
#define clkevt_to_sun5i_timer(x) \
|
||||
container_of(x, struct sun5i_timer, clkevt)
|
||||
|
||||
/*
|
||||
* When we disable a timer, we need to wait at least for 2 cycles of
|
||||
@ -67,30 +55,30 @@ struct sun5i_timer_clkevt {
|
||||
* that is already setup and runs at the same frequency than the other
|
||||
* timers, and we never will be disabled.
|
||||
*/
|
||||
static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
|
||||
static void sun5i_clkevt_sync(struct sun5i_timer *ce)
|
||||
{
|
||||
u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
|
||||
u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1));
|
||||
|
||||
while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
|
||||
while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
|
||||
static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer)
|
||||
{
|
||||
u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
|
||||
writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
|
||||
u32 val = readl(ce->base + TIMER_CTL_REG(timer));
|
||||
writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer));
|
||||
|
||||
sun5i_clkevt_sync(ce);
|
||||
}
|
||||
|
||||
static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
|
||||
static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay)
|
||||
{
|
||||
writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
|
||||
writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer));
|
||||
}
|
||||
|
||||
static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
|
||||
static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic)
|
||||
{
|
||||
u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
|
||||
u32 val = readl(ce->base + TIMER_CTL_REG(timer));
|
||||
|
||||
if (periodic)
|
||||
val &= ~TIMER_CTL_ONESHOT;
|
||||
@ -98,12 +86,12 @@ static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, boo
|
||||
val |= TIMER_CTL_ONESHOT;
|
||||
|
||||
writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
|
||||
ce->timer.base + TIMER_CTL_REG(timer));
|
||||
ce->base + TIMER_CTL_REG(timer));
|
||||
}
|
||||
|
||||
static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
|
||||
{
|
||||
struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
|
||||
struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
|
||||
|
||||
sun5i_clkevt_time_stop(ce, 0);
|
||||
return 0;
|
||||
@ -111,7 +99,7 @@ static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
|
||||
|
||||
static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
|
||||
{
|
||||
struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
|
||||
struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
|
||||
|
||||
sun5i_clkevt_time_stop(ce, 0);
|
||||
sun5i_clkevt_time_start(ce, 0, false);
|
||||
@ -120,10 +108,10 @@ static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
|
||||
|
||||
static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
|
||||
{
|
||||
struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
|
||||
struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
|
||||
|
||||
sun5i_clkevt_time_stop(ce, 0);
|
||||
sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
|
||||
sun5i_clkevt_time_setup(ce, 0, ce->ticks_per_jiffy);
|
||||
sun5i_clkevt_time_start(ce, 0, true);
|
||||
return 0;
|
||||
}
|
||||
@ -131,7 +119,7 @@ static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
|
||||
static int sun5i_clkevt_next_event(unsigned long evt,
|
||||
struct clock_event_device *clkevt)
|
||||
{
|
||||
struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
|
||||
struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
|
||||
|
||||
sun5i_clkevt_time_stop(ce, 0);
|
||||
sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
|
||||
@ -142,9 +130,9 @@ static int sun5i_clkevt_next_event(unsigned long evt,
|
||||
|
||||
static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct sun5i_timer_clkevt *ce = dev_id;
|
||||
struct sun5i_timer *ce = dev_id;
|
||||
|
||||
writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
|
||||
writel(0x1, ce->base + TIMER_IRQ_ST_REG);
|
||||
ce->clkevt.event_handler(&ce->clkevt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
@ -152,17 +140,16 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
|
||||
|
||||
static u64 sun5i_clksrc_read(struct clocksource *clksrc)
|
||||
{
|
||||
struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
|
||||
struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc);
|
||||
|
||||
return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
|
||||
return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1));
|
||||
}
|
||||
|
||||
static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
|
||||
unsigned long event, void *data)
|
||||
static int sun5i_rate_cb(struct notifier_block *nb,
|
||||
unsigned long event, void *data)
|
||||
{
|
||||
struct clk_notifier_data *ndata = data;
|
||||
struct sun5i_timer *timer = to_sun5i_timer(nb);
|
||||
struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
|
||||
struct sun5i_timer *cs = nb_to_sun5i_timer(nb);
|
||||
|
||||
switch (event) {
|
||||
case PRE_RATE_CHANGE:
|
||||
@ -171,6 +158,8 @@ static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
|
||||
|
||||
case POST_RATE_CHANGE:
|
||||
clocksource_register_hz(&cs->clksrc, ndata->new_rate);
|
||||
clockevents_update_freq(&cs->clkevt, ndata->new_rate);
|
||||
cs->ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -180,47 +169,18 @@ static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static int __init sun5i_setup_clocksource(struct device_node *node,
|
||||
void __iomem *base,
|
||||
struct clk *clk, int irq)
|
||||
static int sun5i_setup_clocksource(struct platform_device *pdev,
|
||||
unsigned long rate)
|
||||
{
|
||||
struct sun5i_timer_clksrc *cs;
|
||||
unsigned long rate;
|
||||
struct sun5i_timer *cs = platform_get_drvdata(pdev);
|
||||
void __iomem *base = cs->base;
|
||||
int ret;
|
||||
|
||||
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
|
||||
if (!cs)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret) {
|
||||
pr_err("Couldn't enable parent clock\n");
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
if (!rate) {
|
||||
pr_err("Couldn't get parent clock rate\n");
|
||||
ret = -EINVAL;
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
cs->timer.base = base;
|
||||
cs->timer.clk = clk;
|
||||
cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
|
||||
cs->timer.clk_rate_cb.next = NULL;
|
||||
|
||||
ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
|
||||
if (ret) {
|
||||
pr_err("Unable to register clock notifier.\n");
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
writel(~0, base + TIMER_INTVAL_LO_REG(1));
|
||||
writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
|
||||
base + TIMER_CTL_REG(1));
|
||||
|
||||
cs->clksrc.name = node->name;
|
||||
cs->clksrc.name = pdev->dev.of_node->name;
|
||||
cs->clksrc.rating = 340;
|
||||
cs->clksrc.read = sun5i_clksrc_read;
|
||||
cs->clksrc.mask = CLOCKSOURCE_MASK(32);
|
||||
@ -228,74 +188,23 @@ static int __init sun5i_setup_clocksource(struct device_node *node,
|
||||
|
||||
ret = clocksource_register_hz(&cs->clksrc, rate);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register clock source.\n");
|
||||
goto err_remove_notifier;
|
||||
dev_err(&pdev->dev, "Couldn't register clock source.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_remove_notifier:
|
||||
clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
|
||||
err_disable_clk:
|
||||
clk_disable_unprepare(clk);
|
||||
err_free:
|
||||
kfree(cs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
|
||||
unsigned long event, void *data)
|
||||
static int sun5i_setup_clockevent(struct platform_device *pdev,
|
||||
unsigned long rate, int irq)
|
||||
{
|
||||
struct clk_notifier_data *ndata = data;
|
||||
struct sun5i_timer *timer = to_sun5i_timer(nb);
|
||||
struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
|
||||
|
||||
if (event == POST_RATE_CHANGE) {
|
||||
clockevents_update_freq(&ce->clkevt, ndata->new_rate);
|
||||
ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
|
||||
}
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
|
||||
struct clk *clk, int irq)
|
||||
{
|
||||
struct sun5i_timer_clkevt *ce;
|
||||
unsigned long rate;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sun5i_timer *ce = platform_get_drvdata(pdev);
|
||||
void __iomem *base = ce->base;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ce = kzalloc(sizeof(*ce), GFP_KERNEL);
|
||||
if (!ce)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret) {
|
||||
pr_err("Couldn't enable parent clock\n");
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
if (!rate) {
|
||||
pr_err("Couldn't get parent clock rate\n");
|
||||
ret = -EINVAL;
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
ce->timer.base = base;
|
||||
ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
|
||||
ce->timer.clk = clk;
|
||||
ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
|
||||
ce->timer.clk_rate_cb.next = NULL;
|
||||
|
||||
ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
|
||||
if (ret) {
|
||||
pr_err("Unable to register clock notifier.\n");
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
ce->clkevt.name = node->name;
|
||||
ce->clkevt.name = dev->of_node->name;
|
||||
ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
|
||||
ce->clkevt.set_next_event = sun5i_clkevt_next_event;
|
||||
ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
|
||||
@ -313,60 +222,109 @@ static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem
|
||||
clockevents_config_and_register(&ce->clkevt, rate,
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
|
||||
ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
|
||||
"sun5i_timer0", ce);
|
||||
ret = devm_request_irq(dev, irq, sun5i_timer_interrupt,
|
||||
IRQF_TIMER | IRQF_IRQPOLL,
|
||||
"sun5i_timer0", ce);
|
||||
if (ret) {
|
||||
pr_err("Unable to register interrupt\n");
|
||||
goto err_remove_notifier;
|
||||
dev_err(dev, "Unable to register interrupt\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_remove_notifier:
|
||||
clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
|
||||
err_disable_clk:
|
||||
clk_disable_unprepare(clk);
|
||||
err_free:
|
||||
kfree(ce);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init sun5i_timer_init(struct device_node *node)
|
||||
static int sun5i_timer_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sun5i_timer *st;
|
||||
struct reset_control *rstc;
|
||||
void __iomem *timer_base;
|
||||
struct clk *clk;
|
||||
unsigned long rate;
|
||||
int irq, ret;
|
||||
|
||||
timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
|
||||
if (!st)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, st);
|
||||
|
||||
timer_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(timer_base)) {
|
||||
pr_err("Can't map registers\n");
|
||||
dev_err(dev, "Can't map registers\n");
|
||||
return PTR_ERR(timer_base);
|
||||
}
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (irq <= 0) {
|
||||
pr_err("Can't parse IRQ\n");
|
||||
return -EINVAL;
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "Can't get IRQ\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
clk = of_clk_get(node, 0);
|
||||
clk = devm_clk_get_enabled(dev, NULL);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Can't get timer clock\n");
|
||||
dev_err(dev, "Can't get timer clock\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
rstc = of_reset_control_get(node, NULL);
|
||||
if (!IS_ERR(rstc))
|
||||
rate = clk_get_rate(clk);
|
||||
if (!rate) {
|
||||
dev_err(dev, "Couldn't get parent clock rate\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
st->base = timer_base;
|
||||
st->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
|
||||
st->clk = clk;
|
||||
st->clk_rate_cb.notifier_call = sun5i_rate_cb;
|
||||
st->clk_rate_cb.next = NULL;
|
||||
|
||||
ret = devm_clk_notifier_register(dev, clk, &st->clk_rate_cb);
|
||||
if (ret) {
|
||||
dev_err(dev, "Unable to register clock notifier.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
|
||||
if (rstc)
|
||||
reset_control_deassert(rstc);
|
||||
|
||||
ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
|
||||
ret = sun5i_setup_clocksource(pdev, rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return sun5i_setup_clockevent(node, timer_base, clk, irq);
|
||||
ret = sun5i_setup_clockevent(pdev, rate, irq);
|
||||
if (ret)
|
||||
goto err_unreg_clocksource;
|
||||
|
||||
return 0;
|
||||
|
||||
err_unreg_clocksource:
|
||||
clocksource_unregister(&st->clksrc);
|
||||
return ret;
|
||||
}
|
||||
TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
|
||||
sun5i_timer_init);
|
||||
TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
|
||||
sun5i_timer_init);
|
||||
|
||||
static void sun5i_timer_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sun5i_timer *st = platform_get_drvdata(pdev);
|
||||
|
||||
clocksource_unregister(&st->clksrc);
|
||||
}
|
||||
|
||||
static const struct of_device_id sun5i_timer_of_match[] = {
|
||||
{ .compatible = "allwinner,sun5i-a13-hstimer" },
|
||||
{ .compatible = "allwinner,sun7i-a20-hstimer" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun5i_timer_of_match);
|
||||
|
||||
static struct platform_driver sun5i_timer_driver = {
|
||||
.probe = sun5i_timer_probe,
|
||||
.remove_new = sun5i_timer_remove,
|
||||
.driver = {
|
||||
.name = "sun5i-timer",
|
||||
.of_match_table = sun5i_timer_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun5i_timer_driver);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user