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dt-bindings: clock: keystone: remove unstable remark

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Keystone clock controller bindings were marked as work-in-progress /
unstable in 2013 in commit b9e0d40c0d ("clk: keystone: add Keystone
PLL clock driver") and commit 7affe5685c ("clk: keystone: Add gate
control clock driver") Almost eleven years is enough, so drop the
"unstable" remark and expect usual ABI rules.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240224091236.10146-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2024-02-24 10:12:34 +01:00 committed by Rob Herring
parent a1aa5390cc
commit 438d3fc46f
2 changed files with 0 additions and 4 deletions
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2
Documentation/devicetree/bindings/clock/keystone-gate.txt
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@ -1,5 +1,3 @@
Status: Unstable - ABI compatibility may be broken in the future
Binding for Keystone gate control driver which uses PSC controller IP.
This binding uses the common clock binding[1].

2
Documentation/devicetree/bindings/clock/keystone-pll.txt
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@ -1,5 +1,3 @@
Status: Unstable - ABI compatibility may be broken in the future
Binding for keystone PLLs. The main PLL IP typically has a multiplier,
a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
and PAPLL are controlled by the memory mapped register where as the Main