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clk: imx95: enable the clock of NETCMIX block control

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The NETCMIX block control consists of registers for configuration of
peripherals in the NETC domain, so enable the clock of NETCMIX to
support the configuration.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20240829011849.364987-4-wei.fang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
This commit is contained in:
Wei Fang 2024-08-29 09:18:48 +08:00 committed by Abel Vesa
parent b4f62001cc
commit 42dc425fa8
1 changed files with 30 additions and 0 deletions
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30
drivers/clk/imx/clk-imx95-blk-ctl.c
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@ -248,6 +248,35 @@ static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
.clk_reg_offset = 0,
};
static const struct imx95_blk_ctl_clk_dev_data netxmix_clk_dev_data[] = {
[IMX95_CLK_NETCMIX_ENETC0_RMII] = {
.name = "enetc0_rmii_sel",
.parent_names = (const char *[]){"ext_enetref", "enetref"},
.num_parents = 2,
.reg = 4,
.bit_idx = 5,
.bit_width = 1,
.type = CLK_MUX,
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
},
[IMX95_CLK_NETCMIX_ENETC1_RMII] = {
.name = "enetc1_rmii_sel",
.parent_names = (const char *[]){"ext_enetref", "enetref"},
.num_parents = 2,
.reg = 4,
.bit_idx = 10,
.bit_width = 1,
.type = CLK_MUX,
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
},
};
static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
.num_clks = ARRAY_SIZE(netxmix_clk_dev_data),
.clk_dev_data = netxmix_clk_dev_data,
.clk_reg_offset = 0,
};
static int imx95_bc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -419,6 +448,7 @@ static const struct of_device_id imx95_bc_of_match[] = {
{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
{ /* Sentinel */ },
};
MODULE_DEVICE_TABLE(of, imx95_bc_of_match);