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dt-bindings: pci: xilinx-nwl: Add phys property

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Add phys properties so Linux can power-on/configure the GTR transceivers
(xlnx,zynqmp-psgtr-v1.1).

Link: https://lore.kernel.org/r/20240531161337.864994-2-sean.anderson@linux.dev
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Sean Anderson 2024-05-31 12:13:31 -04:00 committed by Bjorn Helgaas
parent cfd6790397
commit 3e47bcc9b7
1 changed files with 7 additions and 0 deletions
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7
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
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@ -61,6 +61,11 @@ properties:
interrupt-map:
maxItems: 4
phys:
minItems: 1
maxItems: 4
description: One phy per logical lane, in order
power-domains:
maxItems: 1
@ -110,6 +115,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
soc {
#address-cells = <2>;
@ -138,6 +144,7 @@ examples:
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
msi-parent = <&nwl_pcie>;
phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
power-domains = <&zynqmp_firmware PD_PCIE>;
iommus = <&smmu 0x4d0>;
pcie_intc: legacy-interrupt-controller {