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drm/ttm: enable TTM page pool kerneldoc

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Fix the remaining warnings and finally enable this.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210908132933.3269-9-christian.koenig@amd.com
This commit is contained in:
Christian König 2021-09-07 09:42:42 +02:00
parent 4f4859d084
commit 361da7c342
2 changed files with 12 additions and 2 deletions
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9
Documentation/gpu/drm-mm.rst
View File

@ -67,6 +67,15 @@ TTM TT object reference
.. kernel-doc:: drivers/gpu/drm/ttm/ttm_tt.c
:export:
TTM page pool reference
-----------------------
.. kernel-doc:: include/drm/ttm/ttm_pool.h
:internal:
.. kernel-doc:: drivers/gpu/drm/ttm/ttm_pool.c
:export:
The Graphics Execution Manager (GEM)
====================================

5
include/drm/ttm/ttm_pool.h
View File

@ -37,7 +37,7 @@ struct ttm_pool;
struct ttm_operation_ctx;
/**
* ttm_pool_type - Pool for a certain memory type
* struct ttm_pool_type - Pool for a certain memory type
*
* @pool: the pool we belong to, might be NULL for the global ones
* @order: the allocation order our pages have
@ -58,8 +58,9 @@ struct ttm_pool_type {
};
/**
* ttm_pool - Pool for all caching and orders
* struct ttm_pool - Pool for all caching and orders
*
* @dev: the device we allocate pages for
* @use_dma_alloc: if coherent DMA allocations should be used
* @use_dma32: if GFP_DMA32 should be used
* @caching: pools for each caching/order