clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
"acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM driver, but they are the parent clocks for other clocks, in order to use assigned-clock-parents in device tree, the ".fw_name" can't be used, need to assign the clk_hw pointer for the imx8qm_mclk_sels[], imx8qxp_mclk_sels[], imx8dxl_mclk_sels[]. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1720600860-18866-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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@ -54,10 +54,12 @@ struct clk_imx8_acm_sel {
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* struct imx8_acm_soc_data - soc specific data
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* @sels: pointer to struct clk_imx8_acm_sel
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* @num_sels: numbers of items
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* @mclk_sels: pointer to imx8qm/qxp/dxl_mclk_sels
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*/
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struct imx8_acm_soc_data {
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struct clk_imx8_acm_sel *sels;
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unsigned int num_sels;
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struct clk_parent_data *mclk_sels;
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};
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/**
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@ -111,11 +113,14 @@ static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
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{ .fw_name = "sai6_rx_bclk" },
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};
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static const struct clk_parent_data imx8qm_mclk_sels[] = {
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#define ACM_AUD_CLK0_SEL_INDEX 2
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#define ACM_AUD_CLK1_SEL_INDEX 3
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static struct clk_parent_data imx8qm_mclk_sels[] = {
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{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
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{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
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{ .fw_name = "acm_aud_clk0_sel" },
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{ .fw_name = "acm_aud_clk1_sel" },
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{ }, /* clk_hw pointer of "acm_aud_clk0_sel" */
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{ }, /* clk_hw pointer of "acm_aud_clk1_sel" */
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};
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static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
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@ -176,11 +181,11 @@ static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
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{ .fw_name = "sai4_rx_bclk" },
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};
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static const struct clk_parent_data imx8qxp_mclk_sels[] = {
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static struct clk_parent_data imx8qxp_mclk_sels[] = {
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{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
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{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
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{ .fw_name = "acm_aud_clk0_sel" },
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{ .fw_name = "acm_aud_clk1_sel" },
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{ }, /* clk_hw pointer of "acm_aud_clk0_sel" */
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{ }, /* clk_hw pointer of "acm_aud_clk1_sel" */
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};
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static struct clk_imx8_acm_sel imx8qxp_sels[] = {
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@ -228,11 +233,11 @@ static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
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{ .index = -1 },
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};
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static const struct clk_parent_data imx8dxl_mclk_sels[] = {
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static struct clk_parent_data imx8dxl_mclk_sels[] = {
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{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
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{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
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{ .fw_name = "acm_aud_clk0_sel" },
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{ .fw_name = "acm_aud_clk1_sel" },
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{ }, /* clk_hw pointer of "acm_aud_clk0_sel" */
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{ }, /* clk_hw pointer of "acm_aud_clk1_sel" */
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};
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static struct clk_imx8_acm_sel imx8dxl_sels[] = {
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@ -375,6 +380,18 @@ static int imx8_acm_clk_probe(struct platform_device *pdev)
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imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);
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goto err_clk_register;
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}
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/*
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* The IMX_ADMA_ACM_AUD_CLK0_SEL and IMX_ADMA_ACM_AUD_CLK1_SEL are
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* registered first. After registration, update the clk_hw pointer
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* to imx8qm/qxp/dxl_mclk_sels structures.
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*/
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if (sels[i].clkid == IMX_ADMA_ACM_AUD_CLK0_SEL)
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priv->soc_data->mclk_sels[ACM_AUD_CLK0_SEL_INDEX].hw =
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hws[IMX_ADMA_ACM_AUD_CLK0_SEL];
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if (sels[i].clkid == IMX_ADMA_ACM_AUD_CLK1_SEL)
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priv->soc_data->mclk_sels[ACM_AUD_CLK1_SEL_INDEX].hw =
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hws[IMX_ADMA_ACM_AUD_CLK1_SEL];
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
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@ -406,16 +423,19 @@ static void imx8_acm_clk_remove(struct platform_device *pdev)
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static const struct imx8_acm_soc_data imx8qm_acm_data = {
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.sels = imx8qm_sels,
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.num_sels = ARRAY_SIZE(imx8qm_sels),
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.mclk_sels = imx8qm_mclk_sels,
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};
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static const struct imx8_acm_soc_data imx8qxp_acm_data = {
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.sels = imx8qxp_sels,
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.num_sels = ARRAY_SIZE(imx8qxp_sels),
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.mclk_sels = imx8qxp_mclk_sels,
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};
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static const struct imx8_acm_soc_data imx8dxl_acm_data = {
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.sels = imx8dxl_sels,
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.num_sels = ARRAY_SIZE(imx8dxl_sels),
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.mclk_sels = imx8dxl_mclk_sels,
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};
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static const struct of_device_id imx8_acm_match[] = {
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