RISC-V Devicetrees for v6.11
T-Head: Last change from me before this starts going via Drew's tree is the addition of the SBI PMU events node for the th1520. StarFive: A dts for the Pin64 Star64, another board with a jh7110 SoC. This board is almost identical to the existing Milk-v Mars and VisionFive 2 boards that are already support - just with a different PHY configuration and only one of the two PCIe ports exposed. Additionally, the Mars and VisionFive 2 get their PCie configuration added. Microchip: A dts for the BeagleV Fire. PCIe is disabled on it for now, as some binding and driver changes are required. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorVOAAKCRB4tDGHoIJi 0j35AQDgZyo3BkwRVpEqGo4GXNWvOPPfiEAuQ+m8hlnDG8PteQD+LOkcfjK/Y2Bk vj6vhJYGy/9yODRXaI756szEf6VGDg8= =Tefh -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmaL/p0ACgkQYKtH/8kJ UicuDQ/9EQiTkV7dluXIl1/imUBIR1cxqH7nLDjy4A7aC5woNBIPKJA0yDI9DAGn 1hDcQG9zqLNmtpPtfXnlIFMmHoA2DF3UNH+34/RjHkPoweg2J+t+k0SdYL+DRbJi cdLNChYScauZAzOllMLR82Z4k8bBNYAUheF/yMnRL6m928slx1bxYMp7u080VhVA eN3RbLlsvyeifl/wyhH+U7WgQvvJ5WtVfq3bEGjUo26izGTIqh6FBiguBcj0yGvH 5tOT6NKtXfuZQPivo6hDGaedgz6FDjfGBGSk48Cg6arcktHNAeyUNwjIMv19w+si FW8LZiNXFB8l3nVO/CoqjEcwO5Z2dyeJvp7CQSOcJYm/3XoQSnH38nm0Qmf6+NWY pJ3wG0CIbPgSAt2bbumtYW/WRRtrBUEU0de5aZzXGH/iK3aF0bdkQAKj9DOmnc1h 3dhYkxSXPMbtuS6Zf9zvlchiRyN+CnVhAzqQlf4ibQ6NgfHS9c/ZyKsbRbHGRJGm Q5XH/9XgSEp4hCr8/U0e3ZPnuBe1IBfAW2BTVLoKKmWpq/VLqiHvxxrlF9B8ufoU /j0tEGqNSC+aUCFvZtn9FMb+KPaQCqj/qRRuFaLlA2zfrv7PTOl9w6sEa6x3+PoL u/AIvwsZW1ptuN5Ou72gybxOL/zIEd9urchfAZfDQ+6DoXENgTw= =tdm/ -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.11 T-Head: Last change from me before this starts going via Drew's tree is the addition of the SBI PMU events node for the th1520. StarFive: A dts for the Pin64 Star64, another board with a jh7110 SoC. This board is almost identical to the existing Milk-v Mars and VisionFive 2 boards that are already support - just with a different PHY configuration and only one of the two PCIe ports exposed. Additionally, the Mars and VisionFive 2 get their PCie configuration added. Microchip: A dts for the BeagleV Fire. PCIe is disabled on it for now, as some binding and driver changes are required. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: add PCIe dts configuration for JH7110 riscv: dts: microchip: add an initial devicetree for the BeagleV Fire dt-bindings: riscv: microchip: document beaglev-fire riscv: dts: starfive: Update flash partition layout riscv: dts: thead: th1520: Add PMU event node riscv: dts: starfive: add Star64 board devicetree dt-bindings: riscv: starfive: add Star64 board compatible dt-bindings: riscv: Add T-HEAD C908 compatible Link: https://lore.kernel.org/r/20240707-nuttiness-lustfully-4aaf03c991b2@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
31f6b5a651
@ -47,6 +47,7 @@ properties:
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- sifive,u74
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- sifive,u74-mc
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- thead,c906
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- thead,c908
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- thead,c910
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- thead,c920
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- const: riscv
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@ -29,6 +29,7 @@ properties:
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- enum:
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- aldec,tysom-m-mpfs250t-rev2
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- aries,m100pfsevp
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- beagle,beaglev-fire
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- microchip,mpfs-sev-kit
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- sundance,polarberry
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- const: microchip,mpfs
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@ -27,6 +27,7 @@ properties:
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- items:
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- enum:
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- milkv,mars
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- pine64,star64
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- starfive,visionfive-2-v1.2a
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- starfive,visionfive-2-v1.3b
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- const: starfive,jh7110
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@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
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82
arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
Normal file
82
arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
Normal file
@ -0,0 +1,82 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/ {
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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fabric-bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
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<0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
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<0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
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<0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
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<0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
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cape_gpios_p8: gpio@41100000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x41100000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
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"P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
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"P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
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"P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
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};
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cape_gpios_p9: gpio@41200000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x41200000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <20>;
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gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
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"P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
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"P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
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"P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
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"P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
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};
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hsi_gpios: gpio@44000000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x44000000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <20>;
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gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
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"B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
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"B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
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"XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
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"XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
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"XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
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"XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
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};
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};
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refclk_ccc: cccrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_nw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};
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223
arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
Normal file
223
arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
Normal file
@ -0,0 +1,223 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "mpfs.dtsi"
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#include "mpfs-beaglev-fire-fabric.dtsi"
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/* Clock frequency (in Hz) of MTIMER */
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#define MTIMER_FREQ 1000000
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "BeagleBoard BeagleV-Fire";
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compatible = "beagle,beaglev-fire", "microchip,mpfs";
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aliases {
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serial0 = &mmuart0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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serial3 = &mmuart3;
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serial4 = &mmuart4;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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timebase-frequency = <MTIMER_FREQ>;
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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status = "okay";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hss: hss-buffer@103fc00000 {
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compatible = "shared-dma-pool";
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reg = <0x10 0x3fc00000 0x0 0x400000>;
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no-map;
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};
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};
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imx219_clk: camera-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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imx219_vana: fixedregulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "imx219_vana";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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imx219_vdig: fixedregulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "imx219_vdig";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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imx219_vddl: fixedregulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "imx219_vddl";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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};
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&gpio2 {
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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ngpios=<32>;
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gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
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"P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
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"P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
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"P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
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"P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20",
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"P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26",
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"P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1",
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"M2_W_DISABLE2", "VIO_ENABLE", "SD_DET";
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status = "okay";
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vio-enable-hog {
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gpio-hog;
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gpios = <30 30>;
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output-high;
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line-name = "VIO_ENABLE";
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};
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sd-det-hog {
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gpio-hog;
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gpios = <31 31>;
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input;
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line-name = "SD_DET";
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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eeprom: eeprom@50 {
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compatible = "atmel,24c32";
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reg = <0x50>;
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};
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imx219: sensor@10 {
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compatible = "sony,imx219";
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reg = <0x10>;
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clocks = <&imx219_clk>;
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VANA-supply = <&imx219_vana>; /* 2.8v */
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VDIG-supply = <&imx219_vdig>; /* 1.8v */
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VDDL-supply = <&imx219_vddl>; /* 1.2v */
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port {
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imx219_0: endpoint {
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data-lanes = <1 2>;
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clock-noncontinuous;
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link-frequencies = /bits/ 64 <456000000>;
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};
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};
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};
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};
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&mac0 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&mbox {
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status = "okay";
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};
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&mmc {
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bus-width = <4>;
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disable-wp;
|
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
|
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mmc-hs200-1_8v;
|
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sd-uhs-sdr12;
|
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sd-uhs-sdr25;
|
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sd-uhs-sdr50;
|
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sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart0 {
|
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status = "okay";
|
||||
};
|
||||
|
||||
&mmuart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&refclk_ccc {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&syscontroller {
|
||||
microchip,bitstream-flash = <&sys_ctrl_flash>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&syscontroller_qspi {
|
||||
status = "okay";
|
||||
|
||||
sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
spi-rx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
|
||||
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
|
||||
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
|
||||
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
|
||||
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
|
||||
|
||||
@ -294,6 +294,20 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
|
||||
phys = <&pciephy0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
|
||||
phys = <&pciephy1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
};
|
||||
|
||||
&pwmdac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwmdac_pins>;
|
||||
@ -321,16 +335,13 @@
|
||||
#size-cells = <1>;
|
||||
|
||||
spl@0 {
|
||||
reg = <0x0 0x80000>;
|
||||
reg = <0x0 0xf0000>;
|
||||
};
|
||||
uboot-env@f0000 {
|
||||
reg = <0xf0000 0x10000>;
|
||||
};
|
||||
uboot@100000 {
|
||||
reg = <0x100000 0x400000>;
|
||||
};
|
||||
reserved-data@600000 {
|
||||
reg = <0x600000 0xa00000>;
|
||||
reg = <0x100000 0xf00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -476,6 +487,54 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_pins: pcie0-0 {
|
||||
clkreq-pins {
|
||||
pinmux = <GPIOMUX(27, GPOUT_LOW,
|
||||
GPOEN_DISABLE,
|
||||
GPI_NONE)>;
|
||||
bias-pull-down;
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
|
||||
wake-pins {
|
||||
pinmux = <GPIOMUX(32, GPOUT_LOW,
|
||||
GPOEN_DISABLE,
|
||||
GPI_NONE)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_pins: pcie1-0 {
|
||||
clkreq-pins {
|
||||
pinmux = <GPIOMUX(29, GPOUT_LOW,
|
||||
GPOEN_DISABLE,
|
||||
GPI_NONE)>;
|
||||
bias-pull-down;
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
|
||||
wake-pins {
|
||||
pinmux = <GPIOMUX(21, GPOUT_LOW,
|
||||
GPOEN_DISABLE,
|
||||
GPI_NONE)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwmdac_pins: pwmdac-0 {
|
||||
pwmdac-pins {
|
||||
pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
|
||||
|
||||
@ -17,6 +17,13 @@
|
||||
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phy0 {
|
||||
motorcomm,tx-clk-adj-enabled;
|
||||
|
||||
65
arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
Normal file
65
arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
Normal file
@ -0,0 +1,65 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "jh7110-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Pine64 Star64";
|
||||
compatible = "pine64,star64", "starfive,jh7110";
|
||||
aliases {
|
||||
ethernet1 = &gmac1;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
starfive,tx-use-rgmii-clk;
|
||||
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
|
||||
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
starfive,tx-use-rgmii-clk;
|
||||
assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
|
||||
assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phy0 {
|
||||
rx-internal-delay-ps = <1900>;
|
||||
tx-internal-delay-ps = <1500>;
|
||||
motorcomm,rx-clk-drv-microamp = <2910>;
|
||||
motorcomm,rx-data-drv-microamp = <2910>;
|
||||
motorcomm,tx-clk-adj-enabled;
|
||||
motorcomm,tx-clk-10-inverted;
|
||||
motorcomm,tx-clk-100-inverted;
|
||||
motorcomm,tx-clk-1000-inverted;
|
||||
};
|
||||
|
||||
&phy1 {
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <300>;
|
||||
motorcomm,rx-clk-drv-microamp = <2910>;
|
||||
motorcomm,rx-data-drv-microamp = <2910>;
|
||||
motorcomm,tx-clk-adj-enabled;
|
||||
motorcomm,tx-clk-10-inverted;
|
||||
motorcomm,tx-clk-100-inverted;
|
||||
};
|
||||
@ -32,3 +32,11 @@
|
||||
&mmc0 {
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -1214,5 +1214,91 @@
|
||||
#reset-cells = <1>;
|
||||
power-domains = <&pwrc JH7110_PD_VOUT>;
|
||||
};
|
||||
|
||||
pcie0: pcie@940000000 {
|
||||
compatible = "starfive,jh7110-pcie";
|
||||
reg = <0x9 0x40000000 0x0 0x1000000>,
|
||||
<0x0 0x2b000000 0x0 0x100000>;
|
||||
reg-names = "cfg", "apb";
|
||||
linux,pci-domain = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
|
||||
<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
|
||||
interrupts = <56>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
|
||||
<0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
|
||||
<0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
|
||||
<0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
|
||||
msi-controller;
|
||||
device_type = "pci";
|
||||
starfive,stg-syscon = <&stg_syscon>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
|
||||
<&stgcrg JH7110_STGCLK_PCIE0_TL>,
|
||||
<&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
|
||||
<&stgcrg JH7110_STGCLK_PCIE0_APB>;
|
||||
clock-names = "noc", "tl", "axi_mst0", "apb";
|
||||
resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
|
||||
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
|
||||
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
|
||||
<&stgcrg JH7110_STGRST_PCIE0_BRG>,
|
||||
<&stgcrg JH7110_STGRST_PCIE0_CORE>,
|
||||
<&stgcrg JH7110_STGRST_PCIE0_APB>;
|
||||
reset-names = "mst0", "slv0", "slv", "brg",
|
||||
"core", "apb";
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc0: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@9c0000000 {
|
||||
compatible = "starfive,jh7110-pcie";
|
||||
reg = <0x9 0xc0000000 0x0 0x1000000>,
|
||||
<0x0 0x2c000000 0x0 0x100000>;
|
||||
reg-names = "cfg", "apb";
|
||||
linux,pci-domain = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
|
||||
<0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
|
||||
interrupts = <57>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
|
||||
<0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
|
||||
<0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
|
||||
<0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
|
||||
msi-controller;
|
||||
device_type = "pci";
|
||||
starfive,stg-syscon = <&stg_syscon>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
|
||||
<&stgcrg JH7110_STGCLK_PCIE1_TL>,
|
||||
<&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
|
||||
<&stgcrg JH7110_STGCLK_PCIE1_APB>;
|
||||
clock-names = "noc", "tl", "axi_mst0", "apb";
|
||||
resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
|
||||
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
|
||||
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
|
||||
<&stgcrg JH7110_STGRST_PCIE1_BRG>,
|
||||
<&stgcrg JH7110_STGRST_PCIE1_CORE>,
|
||||
<&stgcrg JH7110_STGRST_PCIE1_APB>;
|
||||
reset-names = "mst0", "slv0", "slv", "brg",
|
||||
"core", "apb";
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc1: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -122,6 +122,87 @@
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "riscv,pmu";
|
||||
riscv,event-to-mhpmcounters =
|
||||
<0x00003 0x00003 0x0007fff8>,
|
||||
<0x00004 0x00004 0x0007fff8>,
|
||||
<0x00005 0x00005 0x0007fff8>,
|
||||
<0x00006 0x00006 0x0007fff8>,
|
||||
<0x00007 0x00007 0x0007fff8>,
|
||||
<0x00008 0x00008 0x0007fff8>,
|
||||
<0x00009 0x00009 0x0007fff8>,
|
||||
<0x0000a 0x0000a 0x0007fff8>,
|
||||
<0x10000 0x10000 0x0007fff8>,
|
||||
<0x10001 0x10001 0x0007fff8>,
|
||||
<0x10002 0x10002 0x0007fff8>,
|
||||
<0x10003 0x10003 0x0007fff8>,
|
||||
<0x10010 0x10010 0x0007fff8>,
|
||||
<0x10011 0x10011 0x0007fff8>,
|
||||
<0x10012 0x10012 0x0007fff8>,
|
||||
<0x10013 0x10013 0x0007fff8>;
|
||||
riscv,event-to-mhpmevent =
|
||||
<0x00003 0x00000000 0x00000001>,
|
||||
<0x00004 0x00000000 0x00000002>,
|
||||
<0x00006 0x00000000 0x00000006>,
|
||||
<0x00005 0x00000000 0x00000007>,
|
||||
<0x00007 0x00000000 0x00000008>,
|
||||
<0x00008 0x00000000 0x00000009>,
|
||||
<0x00009 0x00000000 0x0000000a>,
|
||||
<0x0000a 0x00000000 0x0000000b>,
|
||||
<0x10000 0x00000000 0x0000000c>,
|
||||
<0x10001 0x00000000 0x0000000d>,
|
||||
<0x10002 0x00000000 0x0000000e>,
|
||||
<0x10003 0x00000000 0x0000000f>,
|
||||
<0x10010 0x00000000 0x00000010>,
|
||||
<0x10011 0x00000000 0x00000011>,
|
||||
<0x10012 0x00000000 0x00000012>,
|
||||
<0x10013 0x00000000 0x00000013>;
|
||||
riscv,raw-event-to-mhpmcounters =
|
||||
<0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>,
|
||||
<0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>;
|
||||
};
|
||||
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "osc_24m";
|
||||
|
||||
Loading…
Reference in New Issue
Block a user