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crypto: octeontx2 - support setting ctx ilen for inline CPT LF

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Provide an option in Inline IPsec configure mailbox to configure the
CPT_AF_LFX_CTL:CTX_ILEN for inline CPT LF attached to CPT RVU PF.
This is needed to set the ctx ilen to size of inbound SA for
HW errata IPBUCPT-38756. Not setting this would lead to new context's
not being fetched.

Also set FLR_FLUSH in CPT_LF_CTX_CTL for CPT LF's as workaround
for same errata.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Nithin Dabilpuram 2023-12-13 13:00:55 +05:30 committed by Herbert Xu
parent 434c1cb972
commit 3139ebf70a
5 changed files with 61 additions and 1 deletions
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2
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
View File

@ -59,6 +59,8 @@ struct otx2_cpt_rx_inline_lf_cfg {
u32 credit_th;
u16 bpid;
u32 reserved;
u8 ctx_ilen_valid : 1;
u8 ctx_ilen : 7;
};
/*

4
drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
View File

@ -102,6 +102,7 @@
#define OTX2_CPT_LF_Q_INST_PTR (0x110)
#define OTX2_CPT_LF_Q_GRP_PTR (0x120)
#define OTX2_CPT_LF_NQX(a) (0x400 | (a) << 3)
#define OTX2_CPT_LF_CTX_CTL (0x500)
#define OTX2_CPT_LF_CTX_FLUSH (0x510)
#define OTX2_CPT_LF_CTX_ERR (0x520)
#define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT 20
@ -472,7 +473,8 @@ union otx2_cptx_af_lf_ctrl {
u64 cont_err:1;
u64 reserved_11_15:5;
u64 nixtx_en:1;
u64 reserved_17_47:31;
u64 ctx_ilen:3;
u64 reserved_17_47:28;
u64 grp:8;
u64 reserved_56_63:8;
} s;

32
drivers/crypto/marvell/octeontx2/otx2_cptlf.c
View File

@ -106,6 +106,32 @@ static int cptlf_set_grp_and_pri(struct otx2_cptlfs_info *lfs,
return ret;
}
static int cptlf_set_ctx_ilen(struct otx2_cptlfs_info *lfs, int ctx_ilen)
{
union otx2_cptx_af_lf_ctrl lf_ctrl;
struct otx2_cptlf_info *lf;
int slot, ret = 0;
for (slot = 0; slot < lfs->lfs_num; slot++) {
lf = &lfs->lf[slot];
ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,
CPT_AF_LFX_CTL(lf->slot),
&lf_ctrl.u, lfs->blkaddr);
if (ret)
return ret;
lf_ctrl.s.ctx_ilen = ctx_ilen;
ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,
CPT_AF_LFX_CTL(lf->slot),
lf_ctrl.u, lfs->blkaddr);
if (ret)
return ret;
}
return ret;
}
static void cptlf_hw_init(struct otx2_cptlfs_info *lfs)
{
/* Disable instruction queues */
@ -443,6 +469,12 @@ int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri,
if (ret)
goto free_iq;
if (lfs->ctx_ilen_ovrd) {
ret = cptlf_set_ctx_ilen(lfs, lfs->ctx_ilen);
if (ret)
goto free_iq;
}
return 0;
free_iq:

19
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
View File

@ -121,6 +121,8 @@ struct otx2_cptlfs_info {
atomic_t state; /* LF's state. started/reset */
int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */
int global_slot; /* Global slot across the blocks */
u8 ctx_ilen;
u8 ctx_ilen_ovrd;
};
static inline void otx2_cpt_free_instruction_queues(
@ -310,6 +312,19 @@ static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf,
OTX2_CPT_LF_INPROG, lf_inprog.u);
}
static inline void otx2_cptlf_set_ctx_flr_flush(struct otx2_cptlf_info *lf)
{
u8 blkaddr = lf->lfs->blkaddr;
u64 val;
val = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
OTX2_CPT_LF_CTX_CTL);
val |= BIT_ULL(0);
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
OTX2_CPT_LF_CTX_CTL, val);
}
static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf)
{
otx2_cptlf_set_iqueue_exec(lf, true);
@ -325,6 +340,10 @@ static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs)
int slot;
for (slot = 0; slot < lfs->lfs_num; slot++) {
/* Enable flush on FLR for Errata */
if (is_dev_cn10kb(lfs->pdev))
otx2_cptlf_set_ctx_flr_flush(&lfs->lf[slot]);
otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]);
otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]);
}

5
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
View File

@ -267,6 +267,9 @@ static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,
otx2_cptlf_set_dev_info(&cptpf->lfs, cptpf->pdev, cptpf->reg_base,
&cptpf->afpf_mbox, BLKADDR_CPT0);
cptpf->lfs.global_slot = 0;
cptpf->lfs.ctx_ilen_ovrd = cfg_req->ctx_ilen_valid;
cptpf->lfs.ctx_ilen = cfg_req->ctx_ilen;
ret = otx2_inline_cptlf_setup(cptpf, &cptpf->lfs, egrp, num_lfs);
if (ret) {
dev_err(&cptpf->pdev->dev, "Inline-Ipsec CPT0 LF setup failed.\n");
@ -279,6 +282,8 @@ static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,
cptpf->reg_base, &cptpf->afpf_mbox,
BLKADDR_CPT1);
cptpf->cpt1_lfs.global_slot = num_lfs;
cptpf->cpt1_lfs.ctx_ilen_ovrd = cfg_req->ctx_ilen_valid;
cptpf->cpt1_lfs.ctx_ilen = cfg_req->ctx_ilen;
ret = otx2_inline_cptlf_setup(cptpf, &cptpf->cpt1_lfs, egrp,
num_lfs);
if (ret) {