accel/ivpu: Split IP and buttress headers
Move buttress registers to ivpu_hw_btrs_*_reg.h headers. This is an intermediate step before HW layer refactor. Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240515113006.457472-2-jacek.lawrynowicz@linux.intel.com
This commit is contained in:
Wachowski, Karol
Jacek Lawrynowicz
parent
2c3d1bd284
commit
302d583211
@ -5,6 +5,7 @@
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#include "ivpu_drv.h"
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#include "ivpu_fw.h"
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#include "ivpu_hw_btrs_mtl_reg.h"
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#include "ivpu_hw_37xx_reg.h"
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#include "ivpu_hw_reg_io.h"
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#include "ivpu_hw.h"
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@ -54,11 +55,11 @@
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#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
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#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
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(REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR)))
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#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR)) | \
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(REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR)))
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#define BUTTRESS_ALL_IRQ_MASK (BUTTRESS_IRQ_MASK | \
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(REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)))
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(REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE)))
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#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
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#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
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@ -76,11 +77,11 @@ static void ivpu_hw_wa_init(struct ivpu_device *vdev)
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vdev->wa.punit_disabled = false;
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vdev->wa.clear_runtime_mem = false;
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REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK);
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if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) {
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REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK);
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if (REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) {
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/* Writing 1s does not clear the interrupt status register */
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vdev->wa.interrupt_clear_with_0 = true;
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REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);
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REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);
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}
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IVPU_PRINT_WA(punit_disabled);
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@ -100,7 +101,7 @@ static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
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static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
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{
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return REGB_POLL_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
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return REGB_POLL_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
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}
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/* Send KMD initiated workpoint change */
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@ -116,23 +117,23 @@ static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ra
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return ret;
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}
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val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0);
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val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
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val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
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REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
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val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0);
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val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
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val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
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REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, val);
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val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1);
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val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
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val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val);
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REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
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val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1);
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val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
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val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val);
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REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, val);
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val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2);
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val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
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REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
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val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2);
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val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, config, val);
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REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, val);
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val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD);
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val = REG_SET_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, val);
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REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_CMD, val);
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val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_CMD);
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val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val);
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REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_CMD, val);
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ret = ivpu_pll_wait_for_cmd_send(vdev);
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if (ret)
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@ -148,7 +149,7 @@ static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable)
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if (IVPU_WA(punit_disabled))
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return 0;
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return REGB_POLL_FLD(VPU_37XX_BUTTRESS_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US);
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return REGB_POLL_FLD(VPU_HW_BTRS_MTL_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US);
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}
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static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
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@ -156,7 +157,7 @@ static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
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if (IVPU_WA(punit_disabled))
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return 0;
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return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
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return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
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}
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static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
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@ -165,12 +166,12 @@ static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
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u8 fuse_min_ratio, fuse_max_ratio, fuse_pn_ratio;
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u32 fmin_fuse, fmax_fuse;
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fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE);
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fuse_min_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse);
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fuse_pn_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse);
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fmin_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMIN_FUSE);
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fuse_min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
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fuse_pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse);
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fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE);
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fuse_max_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse);
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fmax_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMAX_FUSE);
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fuse_max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
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hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio);
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hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio);
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@ -566,20 +567,20 @@ static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
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int ret;
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u32 val;
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ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
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ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
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if (ret) {
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ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
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return ret;
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}
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val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL);
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val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL);
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if (enable)
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val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val);
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val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
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else
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val = REG_CLR_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val);
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REGB_WR32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, val);
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val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
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REGB_WR32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, val);
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ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
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ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
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if (ret)
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ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
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@ -617,17 +618,17 @@ static int ivpu_hw_37xx_ip_reset(struct ivpu_device *vdev)
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if (IVPU_WA(punit_disabled))
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return 0;
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ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
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ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
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if (ret) {
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ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n");
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return ret;
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}
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val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_IP_RESET);
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val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, val);
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REGB_WR32(VPU_37XX_BUTTRESS_VPU_IP_RESET, val);
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val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_IP_RESET);
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val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, val);
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REGB_WR32(VPU_HW_BTRS_MTL_VPU_IP_RESET, val);
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ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
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ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
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if (ret)
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ivpu_err(vdev, "Timed out waiting for RESET completion\n");
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@ -742,14 +743,14 @@ static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev)
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if (IVPU_WA(punit_disabled))
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return true;
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val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS);
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return REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, val) &&
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REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, val);
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val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_STATUS);
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return REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, val) &&
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REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, val);
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}
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static int ivpu_hw_37xx_wait_for_idle(struct ivpu_device *vdev)
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{
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return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
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return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
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}
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static void ivpu_hw_37xx_save_d0i3_entry_timestamp(struct ivpu_device *vdev)
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@ -826,8 +827,8 @@ static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev)
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{
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u32 pll_curr_ratio;
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pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL);
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pll_curr_ratio &= VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK;
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pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL);
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pll_curr_ratio &= VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK;
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if (!ivpu_is_silicon(vdev))
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return PLL_SIMULATION_FREQ;
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@ -837,17 +838,17 @@ static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev)
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static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
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{
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return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET);
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return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET);
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}
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static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev)
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{
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return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE);
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return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE);
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}
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static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
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{
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return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE);
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return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE);
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}
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static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
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@ -884,14 +885,14 @@ static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev)
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{
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REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);
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REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK);
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REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
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REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
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REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
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REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);
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}
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static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev)
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{
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REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
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REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
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REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);
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REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
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REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
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REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0);
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}
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@ -949,30 +950,30 @@ static bool ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq, bool *w
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/* Handler for IRQs from Buttress core (irqB) */
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static bool ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq)
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{
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u32 status = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
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u32 status = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
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bool schedule_recovery = false;
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if (!status)
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return false;
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if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
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if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status))
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ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x",
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REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL));
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REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL));
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if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) {
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ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
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REGB_WR32(VPU_37XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);
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if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) {
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ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
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REGB_WR32(VPU_HW_BTRS_MTL_ATS_ERR_CLEAR, 0x1);
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schedule_recovery = true;
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}
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if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, status)) {
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u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);
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if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, status)) {
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u32 ufi_log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG);
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ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
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ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log),
|
||||
REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log),
|
||||
REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log));
|
||||
REGB_WR32(VPU_37XX_BUTTRESS_UFI_ERR_CLEAR, 0x1);
|
||||
ufi_log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, ufi_log),
|
||||
REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, ufi_log),
|
||||
REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, ufi_log));
|
||||
REGB_WR32(VPU_HW_BTRS_MTL_UFI_ERR_CLEAR, 0x1);
|
||||
schedule_recovery = true;
|
||||
}
|
||||
|
||||
@ -982,9 +983,9 @@ static bool ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq)
|
||||
* Writing 1 triggers an interrupt, so we can't perform read update write.
|
||||
* Clear local interrupt status by writing 0 to all bits.
|
||||
*/
|
||||
REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);
|
||||
REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);
|
||||
else
|
||||
REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status);
|
||||
REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, status);
|
||||
|
||||
if (schedule_recovery)
|
||||
ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
|
||||
@ -997,13 +998,13 @@ static irqreturn_t ivpu_hw_37xx_irq_handler(int irq, void *ptr)
|
||||
struct ivpu_device *vdev = ptr;
|
||||
bool irqv_handled, irqb_handled, wake_thread = false;
|
||||
|
||||
REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
|
||||
REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);
|
||||
|
||||
irqv_handled = ivpu_hw_37xx_irqv_handler(vdev, irq, &wake_thread);
|
||||
irqb_handled = ivpu_hw_37xx_irqb_handler(vdev, irq);
|
||||
|
||||
/* Re-enable global interrupts to re-trigger MSI for pending interrupts */
|
||||
REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
|
||||
REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);
|
||||
|
||||
if (wake_thread)
|
||||
return IRQ_WAKE_THREAD;
|
||||
@ -1015,7 +1016,7 @@ static irqreturn_t ivpu_hw_37xx_irq_handler(int irq, void *ptr)
|
||||
static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev)
|
||||
{
|
||||
u32 irqv = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
|
||||
u32 irqb = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
|
||||
u32 irqb = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
|
||||
|
||||
if (ivpu_hw_37xx_reg_ipc_rx_count_get(vdev))
|
||||
ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
|
||||
@ -1029,16 +1030,16 @@ static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev)
|
||||
if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv))
|
||||
ivpu_err(vdev, "NOC Firewall irq detected\n");
|
||||
|
||||
if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb))
|
||||
ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, irqb))
|
||||
ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
|
||||
|
||||
if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, irqb)) {
|
||||
u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, irqb)) {
|
||||
u32 ufi_log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG);
|
||||
|
||||
ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
|
||||
ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log),
|
||||
REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log),
|
||||
REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log));
|
||||
ufi_log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, ufi_log),
|
||||
REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, ufi_log),
|
||||
REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, ufi_log));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -8,78 +8,6 @@
|
||||
|
||||
#include <linux/bits.h>
|
||||
|
||||
#define VPU_37XX_BUTTRESS_INTERRUPT_TYPE 0x00000000u
|
||||
|
||||
#define VPU_37XX_BUTTRESS_INTERRUPT_STAT 0x00000004u
|
||||
#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
|
||||
#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
|
||||
#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0 0x00000008u
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1 0x0000000cu
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2 0x00000010u
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_CMD 0x00000014u
|
||||
#define VPU_37XX_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_WP_DOWNLOAD 0x00000018u
|
||||
#define VPU_37XX_BUTTRESS_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_CURRENT_PLL 0x0000001cu
|
||||
#define VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_PLL_ENABLE 0x00000020u
|
||||
|
||||
#define VPU_37XX_BUTTRESS_FMIN_FUSE 0x00000024u
|
||||
#define VPU_37XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
|
||||
#define VPU_37XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_FMAX_FUSE 0x00000028u
|
||||
#define VPU_37XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_TILE_FUSE 0x0000002cu
|
||||
#define VPU_37XX_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0)
|
||||
#define VPU_37XX_BUTTRESS_TILE_FUSE_SKU_MASK GENMASK(3, 2)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_LOCAL_INT_MASK 0x00000030u
|
||||
#define VPU_37XX_BUTTRESS_GLOBAL_INT_MASK 0x00000034u
|
||||
|
||||
#define VPU_37XX_BUTTRESS_PLL_STATUS 0x00000040u
|
||||
#define VPU_37XX_BUTTRESS_PLL_STATUS_LOCK_MASK BIT_MASK(1)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_VPU_STATUS 0x00000044u
|
||||
#define VPU_37XX_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0)
|
||||
#define VPU_37XX_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL 0x00000060u
|
||||
#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
|
||||
#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_VPU_IP_RESET 0x00000050u
|
||||
#define VPU_37XX_BUTTRESS_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000080u
|
||||
#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE 0x00000084u
|
||||
#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000088u
|
||||
|
||||
#define VPU_37XX_BUTTRESS_ATS_ERR_LOG_0 0x000000a0u
|
||||
#define VPU_37XX_BUTTRESS_ATS_ERR_LOG_1 0x000000a4u
|
||||
#define VPU_37XX_BUTTRESS_ATS_ERR_CLEAR 0x000000a8u
|
||||
|
||||
#define VPU_37XX_BUTTRESS_UFI_ERR_LOG 0x000000b0u
|
||||
#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)
|
||||
#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)
|
||||
#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)
|
||||
|
||||
#define VPU_37XX_BUTTRESS_UFI_ERR_CLEAR 0x000000b4u
|
||||
|
||||
#define VPU_37XX_HOST_SS_CPR_CLK_SET 0x00000084u
|
||||
#define VPU_37XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1)
|
||||
#define VPU_37XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10)
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
#include "ivpu_drv.h"
|
||||
#include "ivpu_fw.h"
|
||||
#include "ivpu_hw.h"
|
||||
#include "ivpu_hw_btrs_lnl_reg.h"
|
||||
#include "ivpu_hw_40xx_reg.h"
|
||||
#include "ivpu_hw_reg_io.h"
|
||||
#include "ivpu_ipc.h"
|
||||
@ -58,12 +59,12 @@
|
||||
|
||||
#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
|
||||
|
||||
#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
|
||||
(REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR)) | \
|
||||
(REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR)) | \
|
||||
(REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR)) | \
|
||||
(REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR)) | \
|
||||
(REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR)))
|
||||
#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR)) | \
|
||||
(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR)) | \
|
||||
(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR)) | \
|
||||
(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR)) | \
|
||||
(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR)) | \
|
||||
(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR)))
|
||||
|
||||
#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
|
||||
#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
|
||||
@ -160,7 +161,7 @@ static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
|
||||
|
||||
static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
|
||||
{
|
||||
return REGB_POLL_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
|
||||
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
|
||||
@ -175,24 +176,24 @@ static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ra
|
||||
return ret;
|
||||
}
|
||||
|
||||
val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0);
|
||||
val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
|
||||
val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
|
||||
val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0);
|
||||
val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
|
||||
val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, val);
|
||||
|
||||
val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1);
|
||||
val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
|
||||
val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
|
||||
val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1);
|
||||
val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
|
||||
val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, epp, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, val);
|
||||
|
||||
val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2);
|
||||
val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
|
||||
val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
|
||||
val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2);
|
||||
val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, config, val);
|
||||
val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, cdyn, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, val);
|
||||
|
||||
val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD);
|
||||
val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val);
|
||||
val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_CMD);
|
||||
val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_CMD, val);
|
||||
|
||||
ret = ivpu_pll_wait_for_cmd_send(vdev);
|
||||
if (ret)
|
||||
@ -203,7 +204,7 @@ static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ra
|
||||
|
||||
static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
|
||||
{
|
||||
return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
|
||||
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static int ivpu_wait_for_clock_own_resource_ack(struct ivpu_device *vdev)
|
||||
@ -211,7 +212,7 @@ static int ivpu_wait_for_clock_own_resource_ack(struct ivpu_device *vdev)
|
||||
if (ivpu_is_simics(vdev))
|
||||
return 0;
|
||||
|
||||
return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
|
||||
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
|
||||
}
|
||||
|
||||
static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
|
||||
@ -220,12 +221,12 @@ static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
|
||||
u8 fuse_min_ratio, fuse_pn_ratio, fuse_max_ratio;
|
||||
u32 fmin_fuse, fmax_fuse;
|
||||
|
||||
fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE);
|
||||
fuse_min_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse);
|
||||
fuse_pn_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse);
|
||||
fmin_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMIN_FUSE);
|
||||
fuse_min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
|
||||
fuse_pn_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, PN_RATIO, fmin_fuse);
|
||||
|
||||
fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE);
|
||||
fuse_max_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse);
|
||||
fmax_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMAX_FUSE);
|
||||
fuse_max_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
|
||||
|
||||
hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio);
|
||||
hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio);
|
||||
@ -429,8 +430,8 @@ static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -667,20 +668,20 @@ static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
|
||||
ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
|
||||
if (ret) {
|
||||
ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL);
|
||||
val = REGB_RD32(VPU_HW_BTRS_LNL_D0I3_CONTROL);
|
||||
if (enable)
|
||||
val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
|
||||
val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
|
||||
else
|
||||
val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val);
|
||||
val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_D0I3_CONTROL, val);
|
||||
|
||||
ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
|
||||
ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
|
||||
if (ret) {
|
||||
ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
|
||||
return ret;
|
||||
@ -710,13 +711,13 @@ static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)
|
||||
u32 tile_disable;
|
||||
u32 fuse;
|
||||
|
||||
fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE);
|
||||
if (!REG_TEST_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, VALID, fuse)) {
|
||||
fuse = REGB_RD32(VPU_HW_BTRS_LNL_TILE_FUSE);
|
||||
if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) {
|
||||
ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
tile_disable = REG_GET_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, CONFIG, fuse);
|
||||
tile_disable = REG_GET_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, CONFIG, fuse);
|
||||
if (!ivpu_tile_disable_check(tile_disable)) {
|
||||
ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", tile_disable);
|
||||
return -EIO;
|
||||
@ -751,17 +752,17 @@ static int ivpu_hw_40xx_ip_reset(struct ivpu_device *vdev)
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
|
||||
ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US);
|
||||
if (ret) {
|
||||
ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET);
|
||||
val = REG_SET_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, val);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val);
|
||||
val = REGB_RD32(VPU_HW_BTRS_LNL_IP_RESET);
|
||||
val = REG_SET_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_IP_RESET, val);
|
||||
|
||||
ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
|
||||
ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US);
|
||||
if (ret)
|
||||
ivpu_err(vdev, "Timed out waiting for RESET completion\n");
|
||||
|
||||
@ -817,28 +818,28 @@ static int ivpu_hw_40xx_d0i3_disable(struct ivpu_device *vdev)
|
||||
|
||||
static void ivpu_hw_40xx_profiling_freq_reg_set(struct ivpu_device *vdev)
|
||||
{
|
||||
u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
|
||||
u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
|
||||
|
||||
if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
|
||||
val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
|
||||
val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
|
||||
else
|
||||
val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
|
||||
val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
|
||||
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
|
||||
}
|
||||
|
||||
static void ivpu_hw_40xx_ats_print(struct ivpu_device *vdev)
|
||||
{
|
||||
ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_HM_ATS) ? "Enable" : "Disable");
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_HM_ATS) ? "Enable" : "Disable");
|
||||
}
|
||||
|
||||
static void ivpu_hw_40xx_clock_relinquish_disable(struct ivpu_device *vdev)
|
||||
{
|
||||
u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
|
||||
u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
|
||||
|
||||
val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
|
||||
val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
|
||||
}
|
||||
|
||||
static int ivpu_hw_40xx_power_up(struct ivpu_device *vdev)
|
||||
@ -908,14 +909,14 @@ static bool ivpu_hw_40xx_is_idle(struct ivpu_device *vdev)
|
||||
if (IVPU_WA(punit_disabled))
|
||||
return true;
|
||||
|
||||
val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
|
||||
return REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, val) &&
|
||||
REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, val);
|
||||
val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
|
||||
return REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, val) &&
|
||||
REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, val);
|
||||
}
|
||||
|
||||
static int ivpu_hw_40xx_wait_for_idle(struct ivpu_device *vdev)
|
||||
{
|
||||
return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
|
||||
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static void ivpu_hw_40xx_save_d0i3_entry_timestamp(struct ivpu_device *vdev)
|
||||
@ -979,8 +980,8 @@ static u32 ivpu_hw_40xx_reg_pll_freq_get(struct ivpu_device *vdev)
|
||||
{
|
||||
u32 pll_curr_ratio;
|
||||
|
||||
pll_curr_ratio = REGB_RD32(VPU_40XX_BUTTRESS_PLL_FREQ);
|
||||
pll_curr_ratio &= VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK;
|
||||
pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ);
|
||||
pll_curr_ratio &= VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK;
|
||||
|
||||
return PLL_RATIO_TO_FREQ(pll_curr_ratio);
|
||||
}
|
||||
@ -992,17 +993,17 @@ static u32 ivpu_hw_40xx_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
|
||||
|
||||
static u32 ivpu_hw_40xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET);
|
||||
return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET);
|
||||
}
|
||||
|
||||
static u32 ivpu_hw_40xx_reg_telemetry_size_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE);
|
||||
return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE);
|
||||
}
|
||||
|
||||
static u32 ivpu_hw_40xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
|
||||
{
|
||||
return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE);
|
||||
return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE);
|
||||
}
|
||||
|
||||
static void ivpu_hw_40xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
|
||||
@ -1039,14 +1040,14 @@ static void ivpu_hw_40xx_irq_enable(struct ivpu_device *vdev)
|
||||
{
|
||||
REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);
|
||||
REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);
|
||||
}
|
||||
|
||||
static void ivpu_hw_40xx_irq_disable(struct ivpu_device *vdev)
|
||||
{
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
|
||||
REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
|
||||
REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);
|
||||
}
|
||||
@ -1106,57 +1107,57 @@ static bool ivpu_hw_40xx_irqv_handler(struct ivpu_device *vdev, int irq, bool *w
|
||||
static bool ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq)
|
||||
{
|
||||
bool schedule_recovery = false;
|
||||
u32 status = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
|
||||
u32 status = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
|
||||
|
||||
if (!status)
|
||||
return false;
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status))
|
||||
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE");
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) {
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, status)) {
|
||||
ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1),
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2));
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_ATS_ERR_CLEAR, 0x1);
|
||||
schedule_recovery = true;
|
||||
}
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, status)) {
|
||||
ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR, 0x1);
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, status)) {
|
||||
ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR, 0x1);
|
||||
schedule_recovery = true;
|
||||
}
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, status)) {
|
||||
ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR, 0x1);
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, status)) {
|
||||
ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR, 0x1);
|
||||
schedule_recovery = true;
|
||||
}
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, status)) {
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, status)) {
|
||||
ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR, 0x1);
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW),
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH));
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR, 0x1);
|
||||
schedule_recovery = true;
|
||||
}
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, status)) {
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, status)) {
|
||||
ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR, 0x1);
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW),
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH));
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR, 0x1);
|
||||
schedule_recovery = true;
|
||||
}
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, status)) {
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, status)) {
|
||||
ivpu_err(vdev, "Survivability error detected\n");
|
||||
schedule_recovery = true;
|
||||
}
|
||||
|
||||
/* This must be done after interrupts are cleared at the source. */
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_INTERRUPT_STAT, status);
|
||||
|
||||
if (schedule_recovery)
|
||||
ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
|
||||
@ -1169,13 +1170,13 @@ static irqreturn_t ivpu_hw_40xx_irq_handler(int irq, void *ptr)
|
||||
bool irqv_handled, irqb_handled, wake_thread = false;
|
||||
struct ivpu_device *vdev = ptr;
|
||||
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);
|
||||
|
||||
irqv_handled = ivpu_hw_40xx_irqv_handler(vdev, irq, &wake_thread);
|
||||
irqb_handled = ivpu_hw_40xx_irqb_handler(vdev, irq);
|
||||
|
||||
/* Re-enable global interrupts to re-trigger MSI for pending interrupts */
|
||||
REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
|
||||
REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);
|
||||
|
||||
if (wake_thread)
|
||||
return IRQ_WAKE_THREAD;
|
||||
@ -1187,7 +1188,7 @@ static irqreturn_t ivpu_hw_40xx_irq_handler(int irq, void *ptr)
|
||||
static void ivpu_hw_40xx_diagnose_failure(struct ivpu_device *vdev)
|
||||
{
|
||||
u32 irqv = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
|
||||
u32 irqb = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
|
||||
u32 irqb = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
|
||||
|
||||
if (ivpu_hw_40xx_reg_ipc_rx_count_get(vdev))
|
||||
ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
|
||||
@ -1201,29 +1202,29 @@ static void ivpu_hw_40xx_diagnose_failure(struct ivpu_device *vdev)
|
||||
if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv))
|
||||
ivpu_err(vdev, "NOC Firewall irq detected\n");
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb)) {
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, irqb)) {
|
||||
ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1),
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2));
|
||||
}
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, irqb))
|
||||
ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, irqb))
|
||||
ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, irqb))
|
||||
ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, irqb))
|
||||
ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, irqb))
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, irqb))
|
||||
ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW),
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH));
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, irqb))
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, irqb))
|
||||
ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
|
||||
REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW),
|
||||
REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH));
|
||||
|
||||
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, irqb))
|
||||
if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, irqb))
|
||||
ivpu_err(vdev, "Survivability error detected\n");
|
||||
}
|
||||
|
||||
|
||||
@ -8,91 +8,6 @@
|
||||
|
||||
#include <linux/bits.h>
|
||||
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT 0x00000000u
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2)
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3)
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4)
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5)
|
||||
#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_LOCAL_INT_MASK 0x00000004u
|
||||
#define VPU_40XX_BUTTRESS_GLOBAL_INT_MASK 0x00000008u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_HM_ATS 0x0000000cu
|
||||
|
||||
#define VPU_40XX_BUTTRESS_ATS_ERR_LOG1 0x00000010u
|
||||
#define VPU_40XX_BUTTRESS_ATS_ERR_LOG2 0x00000014u
|
||||
#define VPU_40XX_BUTTRESS_ATS_ERR_CLEAR 0x00000018u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_CFI0_ERR_LOG 0x0000001cu
|
||||
#define VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR 0x00000020u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_CFI1_ERR_LOG 0x00000040u
|
||||
#define VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR 0x00000044u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW 0x00000048u
|
||||
#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH 0x0000004cu
|
||||
#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR 0x00000050u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS 0x00000054u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW 0x00000058u
|
||||
#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH 0x0000005cu
|
||||
#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR 0x00000060u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0 0x00000130u
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1 0x00000134u
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2 0x00000138u
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_CMD 0x0000013cu
|
||||
#define VPU_40XX_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_PLL_FREQ 0x00000148u
|
||||
#define VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK GENMASK(15, 0)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_TILE_FUSE 0x00000150u
|
||||
#define VPU_40XX_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0)
|
||||
#define VPU_40XX_BUTTRESS_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS 0x00000154u
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0)
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1)
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2)
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6)
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7)
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11)
|
||||
#define VPU_40XX_BUTTRESS_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_IP_RESET 0x00000160u
|
||||
#define VPU_40XX_BUTTRESS_IP_RESET_TRIGGER_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_D0I3_CONTROL 0x00000164u
|
||||
#define VPU_40XX_BUTTRESS_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
|
||||
#define VPU_40XX_BUTTRESS_D0I3_CONTROL_I3_MASK BIT_MASK(2)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000168u
|
||||
#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE 0x0000016cu
|
||||
#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000170u
|
||||
|
||||
#define VPU_40XX_BUTTRESS_FMIN_FUSE 0x00000174u
|
||||
#define VPU_40XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
|
||||
#define VPU_40XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
|
||||
|
||||
#define VPU_40XX_BUTTRESS_FMAX_FUSE 0x00000178u
|
||||
#define VPU_40XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
|
||||
|
||||
#define VPU_40XX_HOST_SS_CPR_CLK_EN 0x00000080u
|
||||
#define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK BIT_MASK(1)
|
||||
#define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK BIT_MASK(10)
|
||||
@ -198,6 +113,12 @@
|
||||
#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu
|
||||
#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK BIT_MASK(3)
|
||||
|
||||
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u
|
||||
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0)
|
||||
|
||||
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu
|
||||
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0)
|
||||
|
||||
#define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u
|
||||
#define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0)
|
||||
#define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1)
|
||||
@ -205,6 +126,9 @@
|
||||
#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE 0x00030204u
|
||||
#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE 0x00030210u
|
||||
#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE_REQ_OVERRIDE_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO 0x00040040u
|
||||
#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK BIT_MASK(0)
|
||||
#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1)
|
||||
|
||||
108
drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h
Normal file
108
drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h
Normal file
@ -0,0 +1,108 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020-2024 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __IVPU_HW_BTRS_LNL_REG_H__
|
||||
#define __IVPU_HW_BTRS_LNL_REG_H__
|
||||
|
||||
#include <linux/bits.h>
|
||||
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT 0x00000000u
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2)
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3)
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4)
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5)
|
||||
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_LOCAL_INT_MASK 0x00000004u
|
||||
#define VPU_HW_BTRS_LNL_GLOBAL_INT_MASK 0x00000008u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_HM_ATS 0x0000000cu
|
||||
|
||||
#define VPU_HW_BTRS_LNL_ATS_ERR_LOG1 0x00000010u
|
||||
#define VPU_HW_BTRS_LNL_ATS_ERR_LOG2 0x00000014u
|
||||
#define VPU_HW_BTRS_LNL_ATS_ERR_CLEAR 0x00000018u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_CFI0_ERR_LOG 0x0000001cu
|
||||
#define VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR 0x00000020u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_CFI1_ERR_LOG 0x00000040u
|
||||
#define VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR 0x00000044u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW 0x00000048u
|
||||
#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH 0x0000004cu
|
||||
#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR 0x00000050u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS 0x00000054u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW 0x00000058u
|
||||
#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH 0x0000005cu
|
||||
#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR 0x00000060u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX 0x00000070u
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_CMD_MASK GENMASK(7, 0)
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_PARAM1_MASK GENMASK(15, 8)
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_PARAM2_MASK GENMASK(23, 16)
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_PARAM3_MASK GENMASK(31, 24)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW 0x00000074u
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK GENMASK(7, 0)
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK GENMASK(15, 8)
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK GENMASK(23, 16)
|
||||
#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK GENMASK(31, 24)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0 0x00000130u
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1 0x00000134u
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2 0x00000138u
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_CMD 0x0000013cu
|
||||
#define VPU_HW_BTRS_LNL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_PLL_FREQ 0x00000148u
|
||||
#define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK GENMASK(15, 0)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_TILE_FUSE 0x00000150u
|
||||
#define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK BIT_MASK(0)
|
||||
#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0)
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2)
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6)
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7)
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11)
|
||||
#define VPU_HW_BTRS_LNL_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_IP_RESET 0x00000160u
|
||||
#define VPU_HW_BTRS_LNL_IP_RESET_TRIGGER_MASK BIT_MASK(0)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_D0I3_CONTROL 0x00000164u
|
||||
#define VPU_HW_BTRS_LNL_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
|
||||
#define VPU_HW_BTRS_LNL_D0I3_CONTROL_I3_MASK BIT_MASK(2)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET 0x00000168u
|
||||
#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE 0x0000016cu
|
||||
#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE 0x00000170u
|
||||
|
||||
#define VPU_HW_BTRS_LNL_FMIN_FUSE 0x00000174u
|
||||
#define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
|
||||
#define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
|
||||
|
||||
#define VPU_HW_BTRS_LNL_FMAX_FUSE 0x00000178u
|
||||
#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
|
||||
|
||||
#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */
|
||||
83
drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
Normal file
83
drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
Normal file
@ -0,0 +1,83 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020-2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __IVPU_HW_BTRS_MTL_REG_H__
|
||||
#define __IVPU_HW_BTRS_MTL_REG_H__
|
||||
|
||||
#include <linux/bits.h>
|
||||
|
||||
#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE 0x00000000u
|
||||
|
||||
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT 0x00000004u
|
||||
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
|
||||
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
|
||||
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2)
|
||||
|
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 0x00000008u
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 0x0000000cu
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 0x00000010u
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#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_MTL_WP_REQ_CMD 0x00000014u
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#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
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#define VPU_HW_BTRS_MTL_WP_DOWNLOAD 0x00000018u
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#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_MTL_CURRENT_PLL 0x0000001cu
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#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_MTL_PLL_ENABLE 0x00000020u
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#define VPU_HW_BTRS_MTL_FMIN_FUSE 0x00000024u
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#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
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#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
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|
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#define VPU_HW_BTRS_MTL_FMAX_FUSE 0x00000028u
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#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
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|
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#define VPU_HW_BTRS_MTL_TILE_FUSE 0x0000002cu
|
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#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK BIT_MASK(0)
|
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#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2)
|
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|
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#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK 0x00000030u
|
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#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK 0x00000034u
|
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|
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#define VPU_HW_BTRS_MTL_PLL_STATUS 0x00000040u
|
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#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK BIT_MASK(1)
|
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|
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#define VPU_HW_BTRS_MTL_VPU_STATUS 0x00000044u
|
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#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK BIT_MASK(0)
|
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#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
|
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|
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#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL 0x00000060u
|
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#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
|
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#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2)
|
||||
|
||||
#define VPU_HW_BTRS_MTL_VPU_IP_RESET 0x00000050u
|
||||
#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0)
|
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|
||||
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET 0x00000080u
|
||||
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE 0x00000084u
|
||||
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE 0x00000088u
|
||||
|
||||
#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 0x000000a0u
|
||||
#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 0x000000a4u
|
||||
#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR 0x000000a8u
|
||||
|
||||
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG 0x000000b0u
|
||||
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)
|
||||
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)
|
||||
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)
|
||||
|
||||
#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR 0x000000b4u
|
||||
|
||||
#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */
|
||||
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Reference in New Issue
Block a user