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dt-bindings: xilinx: replace Piyush Mehta maintainership

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As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
Xilinx udc controller maintainership duties to Mubin and Radhey.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Mubin Sayyed <mubin.sayyed@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Piyush Mehta <piyush.mehta@amd.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/1705664181-722937-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Radhey Shyam Pandey 2024-01-19 17:06:21 +05:30 committed by Rob Herring
parent 6154fb9c21
commit 2d3b3ab8d0
6 changed files with 12 additions and 6 deletions
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3
Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
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@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some

3
Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
View File

@ -12,7 +12,8 @@ description:
PS_MODE). Every pin can be configured as input/output.
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible:

3
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
View File

@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zynq UltraScale+ MPSoC and Versal reset
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |
The Zynq UltraScale+ MPSoC and Versal has several different resets.

3
Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
View File

@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx SuperSpeed DWC3 USB SoC controller
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible:

3
Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
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@ -16,8 +16,9 @@ description:
USB 2.0 traffic.
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
- Michal Simek <michal.simek@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible:

3
Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
View File

@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx udc controller
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible: