spi: pxa2xx: Remove outdated documentation
The documentation is referring to the legacy enumeration of the SPI host controllers and target devices. It has nothing to do with the modern way, which is the only supported in kernel right now. Hence, remove outdated documentation file. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240417110334.2671228-5-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Andy Shevchenko
Mark Brown
parent
2a45166938
commit
2d069c11e8
@ -1,208 +0,0 @@
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==============================
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PXA2xx SPI on SSP driver HOWTO
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==============================
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This a mini HOWTO on the pxa2xx_spi driver. The driver turns a PXA2xx
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synchronous serial port into an SPI host controller
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(see Documentation/spi/spi-summary.rst). The driver has the following features
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- Support for any PXA2xx and compatible SSP.
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- SSP PIO and SSP DMA data transfers.
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- External and Internal (SSPFRM) chip selects.
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- Per peripheral device (chip) configuration.
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- Full suspend, freeze, resume support.
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The driver is built around a &struct spi_message FIFO serviced by kernel
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thread. The kernel thread, spi_pump_messages(), drives message FIFO and
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is responsible for queuing SPI transactions and setting up and launching
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the DMA or interrupt driven transfers.
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Declaring PXA2xx host controllers
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---------------------------------
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Typically, for a legacy platform, an SPI host controller is defined in the
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arch/.../mach-*/board-*.c as a "platform device". The host controller configuration
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is passed to the driver via a table found in include/linux/spi/pxa2xx_spi.h::
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struct pxa2xx_spi_controller {
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u8 num_chipselect;
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u8 enable_dma;
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...
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};
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The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
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peripheral devices (chips) attached to this SPI host controller.
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The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
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be used. This caused the driver to acquire two DMA channels: Rx channel and
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Tx channel. The Rx channel has a higher DMA service priority than the Tx channel.
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See the "PXA2xx Developer Manual" section "DMA Controller".
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For the new platforms the description of the controller and peripheral devices
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comes from Device Tree or ACPI.
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NSSP HOST SAMPLE
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----------------
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Below is a sample configuration using the PXA255 NSSP for a legacy platform::
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static struct resource pxa_spi_nssp_resources[] = {
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[0] = {
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.start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
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.end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_NSSP, /* NSSP IRQ */
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.end = IRQ_NSSP,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct pxa2xx_spi_controller pxa_nssp_controller_info = {
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.num_chipselect = 1, /* Matches the number of chips attached to NSSP */
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.enable_dma = 1, /* Enables NSSP DMA */
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};
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static struct platform_device pxa_spi_nssp = {
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.name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
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.id = 2, /* Bus number, MUST MATCH SSP number 1..n */
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.resource = pxa_spi_nssp_resources,
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.num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
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.dev = {
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.platform_data = &pxa_nssp_controller_info, /* Passed to driver */
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},
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};
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static struct platform_device *devices[] __initdata = {
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&pxa_spi_nssp,
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};
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static void __init board_init(void)
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{
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(void)platform_add_device(devices, ARRAY_SIZE(devices));
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}
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Declaring peripheral devices
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----------------------------
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Typically, for a legacy platform, each SPI peripheral device (chip) is defined in the
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arch/.../mach-*/board-*.c using the "spi_board_info" structure found in
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"linux/spi/spi.h". See "Documentation/spi/spi-summary.rst" for additional
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information.
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Each peripheral device (chip) attached to the PXA2xx must provide specific chip configuration
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information via the structure "pxa2xx_spi_chip" found in
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"include/linux/spi/pxa2xx_spi.h". The PXA2xx host controller driver will use
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the configuration whenever the driver communicates with the peripheral
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device. All fields are optional.
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::
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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u8 rx_threshold;
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u8 dma_burst_size;
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u32 timeout;
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};
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The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
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used to configure the SSP hardware FIFO. These fields are critical to the
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performance of pxa2xx_spi driver and misconfiguration will result in rx
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FIFO overruns (especially in PIO mode transfers). Good default values are::
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.tx_threshold = 8,
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.rx_threshold = 8,
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The range is 1 to 16 where zero indicates "use default".
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The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
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engine and is related the "spi_device.bits_per_word" field. Read and understand
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the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
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to determine the correct value. An SSP configured for byte-wide transfers would
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use a value of 8. The driver will determine a reasonable default if
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dma_burst_size == 0.
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The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
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trailing bytes in the SSP receiver FIFO. The correct value for this field is
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dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
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peripheral device. Please note that the PXA2xx SSP 1 does not support trailing byte
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timeouts and must busy-wait any trailing bytes.
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NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
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chipselect is dropped after each spi_transfer. Most devices need chip select
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asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor)
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to accommodate these chips.
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NSSP PERIPHERAL SAMPLE
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----------------------
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For a legacy platform or in some other cases, the pxa2xx_spi_chip structure
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is passed to the pxa2xx_spi driver in the "spi_board_info.controller_data"
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field. Below is a sample configuration using the PXA255 NSSP.
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::
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static struct pxa2xx_spi_chip cs8415a_chip_info = {
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.tx_threshold = 8, /* SSP hardware FIFO threshold */
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.rx_threshold = 8, /* SSP hardware FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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};
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static struct pxa2xx_spi_chip cs8405a_chip_info = {
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.tx_threshold = 8, /* SSP hardware FIFO threshold */
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.rx_threshold = 8, /* SSP hardware FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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};
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static struct spi_board_info streetracer_spi_board_info[] __initdata = {
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{
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.modalias = "cs8415a", /* Name of spi_driver for this device */
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.max_speed_hz = 3686400, /* Run SSP as fast a possible */
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.bus_num = 2, /* Framework bus number */
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.chip_select = 0, /* Framework chip select */
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.platform_data = NULL; /* No spi_driver specific config */
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.controller_data = &cs8415a_chip_info, /* Host controller config */
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.irq = STREETRACER_APCI_IRQ, /* Peripheral device interrupt */
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},
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{
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.modalias = "cs8405a", /* Name of spi_driver for this device */
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.max_speed_hz = 3686400, /* Run SSP as fast a possible */
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.bus_num = 2, /* Framework bus number */
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.chip_select = 1, /* Framework chip select */
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.controller_data = &cs8405a_chip_info, /* Host controller config */
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.irq = STREETRACER_APCI_IRQ, /* Peripheral device interrupt */
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},
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};
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static void __init streetracer_init(void)
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{
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spi_register_board_info(streetracer_spi_board_info,
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ARRAY_SIZE(streetracer_spi_board_info));
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}
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DMA and PIO I/O Support
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-----------------------
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The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
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transfers. The driver defaults to PIO mode and DMA transfers must be enabled
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by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure.
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For the newer platforms, that are known to support DMA, the driver will enable
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it automatically and try it first with a possible fallback to PIO. The DMA
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mode supports both coherent and stream based DMA mappings.
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The following logic is used to determine the type of I/O to be used on
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a per "spi_transfer" basis::
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if spi_message.len > 65536 then
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print "rate limited" warning
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use PIO transfers
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if enable_dma and the size is in the range [DMA burst size..65536] then
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use streaming DMA mode
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otherwise
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use PIO transfer
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THANKS TO
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---------
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David Brownell and others for mentoring the development of this driver.
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@ -832,8 +832,7 @@ config SPI_PXA2XX
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select PXA_SSP if ARCH_PXA || ARCH_MMP
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help
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This enables using a PXA2xx or Sodaville SSP port as a SPI master
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controller. The driver can be configured to use any SSP port and
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additional documentation can be found a Documentation/spi/pxa2xx.rst.
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controller. The driver can be configured to use any SSP port.
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config SPI_PXA2XX_PCI
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def_tristate SPI_PXA2XX && PCI && COMMON_CLK
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