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ASoC: Merge up fixes

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Merge branch 'for-6.11' of
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into
asoc-6.12 for some AMD work.
This commit is contained in:
Mark Brown 2024-08-20 15:23:08 +01:00
commit 2c9abde403
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GPG Key ID: 24D68B725D5487D0
13 changed files with 70 additions and 25 deletions
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1
MAINTAINERS
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@ -18526,7 +18526,6 @@ F: drivers/crypto/intel/qat/
QCOM AUDIO (ASoC) DRIVERS
M: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
M: Banajit Goswami <bgoswami@quicinc.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
L: linux-arm-msm@vger.kernel.org
S: Supported

2
sound/soc/amd/acp/acp-legacy-mach.c
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@ -227,6 +227,8 @@ static const struct platform_device_id board_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(platform, board_ids);
static struct platform_driver acp_asoc_audio = {
.driver = {
.pm = &snd_soc_pm_ops,

6
sound/soc/codecs/lpass-macro-common.h
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@ -49,6 +49,12 @@ static inline void lpass_macro_pds_exit_action(void *pds)
static inline const char *lpass_macro_get_codec_version_string(int version)
{
switch (version) {
case LPASS_CODEC_VERSION_1_0:
return "v1.0";
case LPASS_CODEC_VERSION_1_1:
return "v1.1";
case LPASS_CODEC_VERSION_1_2:
return "v1.2";
case LPASS_CODEC_VERSION_2_0:
return "v2.0";
case LPASS_CODEC_VERSION_2_1:

4
sound/soc/codecs/lpass-va-macro.c
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@ -1485,6 +1485,10 @@ static void va_macro_set_lpass_codec_version(struct va_macro *va)
if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x80 || core_id_2 == 0x81))
version = LPASS_CODEC_VERSION_2_8;
if (version == LPASS_CODEC_VERSION_UNKNOWN)
dev_warn(va->dev, "Unknown Codec version, ID: %02x / %02x / %02x\n",
core_id_0, core_id_1, core_id_2);
lpass_macro_set_codec_version(version);
dev_dbg(va->dev, "LPASS Codec Version %s\n", lpass_macro_get_codec_version_string(version));

5
sound/soc/codecs/wcd937x.c
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@ -242,10 +242,9 @@ static const struct regmap_irq_chip wcd937x_regmap_irq_chip = {
static void wcd937x_reset(struct wcd937x_priv *wcd937x)
{
usleep_range(20, 30);
gpiod_set_value(wcd937x->reset_gpio, 1);
usleep_range(20, 30);
gpiod_set_value(wcd937x->reset_gpio, 0);
usleep_range(20, 30);
}

1
sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
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@ -2748,6 +2748,7 @@ static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
case AFE_ASRC12_NEW_CON9:
case AFE_LRCK_CNT:
case AFE_DAC_MON0:
case AFE_DAC_CON0:
case AFE_DL2_CUR:
case AFE_DL3_CUR:
case AFE_DL6_CUR:

6
sound/soc/sof/amd/acp-dsp-offset.h
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@ -76,13 +76,15 @@
#define DSP_SW_INTR_CNTL_OFFSET 0x0
#define DSP_SW_INTR_STAT_OFFSET 0x4
#define DSP_SW_INTR_TRIG_OFFSET 0x8
#define ACP_ERROR_STATUS 0x18C4
#define ACP3X_ERROR_STATUS 0x18C4
#define ACP6X_ERROR_STATUS 0x1A4C
#define ACP3X_AXI2DAGB_SEM_0 0x1880
#define ACP5X_AXI2DAGB_SEM_0 0x1884
#define ACP6X_AXI2DAGB_SEM_0 0x1874
/* ACP common registers to report errors related to I2S & SoundWire interfaces */
#define ACP_SW0_I2S_ERROR_REASON 0x18B4
#define ACP3X_SW_I2S_ERROR_REASON 0x18C8
#define ACP6X_SW0_I2S_ERROR_REASON 0x18B4
#define ACP_SW1_I2S_ERROR_REASON 0x1A50
/* Registers from ACP_SHA block */

52
sound/soc/sof/amd/acp.c
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@ -92,6 +92,7 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
unsigned int idx, unsigned int dscr_count)
{
struct snd_sof_dev *sdev = adata->dev;
const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
unsigned int val, status;
int ret;
@ -102,7 +103,7 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
val & (1 << ch), ACP_REG_POLL_INTERVAL,
ACP_REG_POLL_TIMEOUT_US);
if (ret < 0) {
status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
@ -263,6 +264,17 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
/* psp_send_cmd only required for vangogh platform (rev - 5) */
if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) {
/* Modify IRAM and DRAM size */
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);
if (ret)
return ret;
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);
if (ret)
return ret;
}
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
@ -280,17 +292,6 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
return ret;
}
/* psp_send_cmd only required for vangogh platform (rev - 5) */
if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) {
/* Modify IRAM and DRAM size */
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);
if (ret)
return ret;
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);
if (ret)
return ret;
}
ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,
fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,
ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
@ -402,9 +403,11 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_id)
if (val & ACP_ERROR_IRQ_MASK) {
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0);
/* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */
if (desc->rev >= 6)
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0);
irq_flag = 1;
}
@ -430,6 +433,7 @@ static int acp_power_on(struct snd_sof_dev *sdev)
const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
unsigned int base = desc->pgfsm_base;
unsigned int val;
unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask;
int ret;
val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
@ -437,9 +441,23 @@ static int acp_power_on(struct snd_sof_dev *sdev)
if (val == ACP_POWERED_ON)
return 0;
if (val & ACP_PGFSM_STATUS_MASK)
switch (desc->rev) {
case 3:
case 5:
acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;
acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;
break;
case 6:
acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
break;
default:
return -EINVAL;
}
if (val & acp_pgfsm_status_mask)
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
ACP_PGFSM_CNTL_POWER_ON_MASK);
acp_pgfsm_cntl_mask);
ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
!val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);

9
sound/soc/sof/amd/acp.h
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@ -25,8 +25,11 @@
#define ACP_REG_POLL_TIMEOUT_US 2000
#define ACP_DMA_COMPLETE_TIMEOUT_US 5000
#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
#define ACP_PGFSM_STATUS_MASK 0x03
#define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01
#define ACP3X_PGFSM_STATUS_MASK 0x03
#define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07
#define ACP6X_PGFSM_STATUS_MASK 0x0F
#define ACP_POWERED_ON 0x00
#define ACP_ASSERT_RESET 0x01
#define ACP_RELEASE_RESET 0x00
@ -203,6 +206,8 @@ struct sof_amd_acp_desc {
u32 probe_reg_offset;
u32 reg_start_addr;
u32 reg_end_addr;
u32 acp_error_stat;
u32 acp_sw0_i2s_err_reason;
u32 sdw_max_link_count;
u64 sdw_acpi_dev_addr;
};

2
sound/soc/sof/amd/pci-acp63.c
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@ -35,6 +35,8 @@ static const struct sof_amd_acp_desc acp63_chip_info = {
.ext_intr_cntl = ACP6X_EXTERNAL_INTR_CNTL,
.ext_intr_stat = ACP6X_EXT_INTR_STAT,
.ext_intr_stat1 = ACP6X_EXT_INTR_STAT1,
.acp_error_stat = ACP6X_ERROR_STATUS,
.acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON,
.dsp_intr_base = ACP6X_DSP_SW_INTR_BASE,
.sram_pte_offset = ACP6X_SRAM_PTE_OFFSET,
.hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,

2
sound/soc/sof/amd/pci-rmb.c
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@ -33,6 +33,8 @@ static const struct sof_amd_acp_desc rembrandt_chip_info = {
.pgfsm_base = ACP6X_PGFSM_BASE,
.ext_intr_stat = ACP6X_EXT_INTR_STAT,
.dsp_intr_base = ACP6X_DSP_SW_INTR_BASE,
.acp_error_stat = ACP6X_ERROR_STATUS,
.acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON,
.sram_pte_offset = ACP6X_SRAM_PTE_OFFSET,
.hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,
.fusion_dsp_offset = ACP6X_DSP_FUSION_RUNSTALL,

2
sound/soc/sof/amd/pci-rn.c
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@ -33,6 +33,8 @@ static const struct sof_amd_acp_desc renoir_chip_info = {
.pgfsm_base = ACP3X_PGFSM_BASE,
.ext_intr_stat = ACP3X_EXT_INTR_STAT,
.dsp_intr_base = ACP3X_DSP_SW_INTR_BASE,
.acp_error_stat = ACP3X_ERROR_STATUS,
.acp_sw0_i2s_err_reason = ACP3X_SW_I2S_ERROR_REASON,
.sram_pte_offset = ACP3X_SRAM_PTE_OFFSET,
.hw_semaphore_offset = ACP3X_AXI2DAGB_SEM_0,
.acp_clkmux_sel = ACP3X_CLKMUX_SEL,

3
sound/soc/sof/mediatek/mt8195/mt8195.c
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@ -574,6 +574,9 @@ static struct snd_sof_of_mach sof_mt8195_machs[] = {
{
.compatible = "google,tomato",
.sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682.tplg"
}, {
.compatible = "google,dojo",
.sof_tplg_filename = "sof-mt8195-mt6359-max98390-rt5682.tplg"
}, {
.compatible = "mediatek,mt8195",
.sof_tplg_filename = "sof-mt8195.tplg"