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phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk

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In preparation for support for additional platforms, convert the phy
register access clock to using the clk_bulk interfaces.

Newer SoCs like Google Tensor gs101 require additional clocks for
access to additional (different) register areas (PHY, PMA, PCS), and
converting to clk_bulk simplifies addition of those extra clocks.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
André Draszik 2024-06-17 17:44:45 +01:00 committed by Vinod Koul
parent 54290bd981
commit 26ba326121
1 changed files with 39 additions and 15 deletions
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54
drivers/phy/samsung/phy-exynos5-usbdrd.c
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@ -185,6 +185,8 @@ struct exynos5_usbdrd_phy_config {
struct exynos5_usbdrd_phy_drvdata {
const struct exynos5_usbdrd_phy_config *phy_cfg;
const struct phy_ops *phy_ops;
const char * const *clk_names;
int n_clks;
const char * const *core_clk_names;
int n_core_clks;
u32 pmu_offset_usbdrd0_phy;
@ -196,7 +198,7 @@ struct exynos5_usbdrd_phy_drvdata {
* struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
* @dev: pointer to device instance of this platform device
* @reg_phy: usb phy controller register memory base
* @clk: phy clock for register access
* @clks: clocks for register access
* @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
* @drv_data: pointer to SoC level driver data structure
* @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
@ -209,7 +211,7 @@ struct exynos5_usbdrd_phy_drvdata {
struct exynos5_usbdrd_phy {
struct device *dev;
void __iomem *reg_phy;
struct clk *clk;
struct clk_bulk_data *clks;
struct clk_bulk_data *core_clks;
const struct exynos5_usbdrd_phy_drvdata *drv_data;
struct phy_usb_instance {
@ -402,7 +404,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
struct phy_usb_instance *inst = phy_get_drvdata(phy);
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
ret = clk_prepare_enable(phy_drd->clk);
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
if (ret)
return ret;
@ -452,7 +454,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
reg &= ~PHYCLKRST_PORTRESET;
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
clk_disable_unprepare(phy_drd->clk);
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
return 0;
}
@ -464,7 +466,7 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy)
struct phy_usb_instance *inst = phy_get_drvdata(phy);
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
ret = clk_prepare_enable(phy_drd->clk);
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
if (ret)
return ret;
@ -486,7 +488,7 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy)
PHYTEST_POWERDOWN_HSP;
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
clk_disable_unprepare(phy_drd->clk);
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
return 0;
}
@ -811,14 +813,14 @@ static int exynos850_usbdrd_phy_init(struct phy *phy)
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
int ret;
ret = clk_prepare_enable(phy_drd->clk);
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
if (ret)
return ret;
/* UTMI or PIPE3 specific init */
inst->phy_cfg->phy_init(phy_drd);
clk_disable_unprepare(phy_drd->clk);
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
return 0;
}
@ -831,7 +833,7 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy)
u32 reg;
int ret;
ret = clk_prepare_enable(phy_drd->clk);
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
if (ret)
return ret;
@ -854,7 +856,7 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy)
reg &= ~CLKRST_LINK_SW_RST;
writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
clk_disable_unprepare(phy_drd->clk);
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
return 0;
}
@ -873,11 +875,19 @@ static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
struct clk *ref_clk;
unsigned long ref_rate;
phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
if (IS_ERR(phy_drd->clk)) {
dev_err(phy_drd->dev, "Failed to get phy clock\n");
return PTR_ERR(phy_drd->clk);
}
phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks,
sizeof(*phy_drd->clks), GFP_KERNEL);
if (!phy_drd->clks)
return -ENOMEM;
for (int i = 0; i < phy_drd->drv_data->n_clks; ++i)
phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i];
ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks,
phy_drd->clks);
if (ret)
return dev_err_probe(phy_drd->dev, ret,
"failed to get phy clock(s)\n");
phy_drd->core_clks = devm_kcalloc(phy_drd->dev,
phy_drd->drv_data->n_core_clks,
@ -939,6 +949,10 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = {
},
};
static const char * const exynos5_clk_names[] = {
"phy",
};
static const char * const exynos5_core_clk_names[] = {
"ref",
};
@ -952,6 +966,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
.phy_ops = &exynos5_usbdrd_phy_ops,
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
.pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
.clk_names = exynos5_clk_names,
.n_clks = ARRAY_SIZE(exynos5_clk_names),
.core_clk_names = exynos5_core_clk_names,
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
};
@ -960,6 +976,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
.phy_cfg = phy_cfg_exynos5,
.phy_ops = &exynos5_usbdrd_phy_ops,
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
.clk_names = exynos5_clk_names,
.n_clks = ARRAY_SIZE(exynos5_clk_names),
.core_clk_names = exynos5_core_clk_names,
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
};
@ -969,6 +987,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = {
.phy_ops = &exynos5_usbdrd_phy_ops,
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
.pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL,
.clk_names = exynos5_clk_names,
.n_clks = ARRAY_SIZE(exynos5_clk_names),
.core_clk_names = exynos5433_core_clk_names,
.n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
};
@ -977,6 +997,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
.phy_cfg = phy_cfg_exynos5,
.phy_ops = &exynos5_usbdrd_phy_ops,
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
.clk_names = exynos5_clk_names,
.n_clks = ARRAY_SIZE(exynos5_clk_names),
.core_clk_names = exynos5433_core_clk_names,
.n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
};
@ -985,6 +1007,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
.phy_cfg = phy_cfg_exynos850,
.phy_ops = &exynos850_usbdrd_phy_ops,
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
.clk_names = exynos5_clk_names,
.n_clks = ARRAY_SIZE(exynos5_clk_names),
.core_clk_names = exynos5_core_clk_names,
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
};