intel-pinctrl for v6.12-1
* Enable High Impedance pin configuration support for Intel pin control * Miscellaneous small improvements here and there The following is an automated git shortlog grouped by driver: baytrail: - Drop duplicate return statement intel: - Constify struct intel_pinctrl parameter - Inline intel_gpio_community_irq_handler() - Introduce for_each_intel_gpio_group() helper et al. - Constify intel_get_community() returned object - Implement high impedance support - Add __intel_gpio_get_direction() helper - Refactor __intel_gpio_set_direction() to be more useful - Move debounce validation out of the lock -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEhiZOUlnC9oKN3n3AmT3/83c5Sy0FAmbgAl8ACgkQmT3/83c5 Sy3XhQ//WfkhNv73IVvGPlKLI4s6A43xINEZ/8gVNeukaOGIi54xu3wlV5QevDOS 6MacKg0g0ZUo1KQXp86o54LqvCfOLklFzJsiWkYXqqImRvuA+5OuP4fVOv3XV9Ga i1b07A4vFamHwzUKt5kTYwhPOcqNzwYmPgU3jcArpANFs3lahVA9zCCzyXURTNnQ UH546mEqDezH2m5WgDHATBakSRJJr9bsVYIwAO/8OOz+V75Spmag0vJgWY/9QQms 3mUoJmTLOQbaDUqVqvTRU0uovgUlYXIOJS2EWLqnFBcK78fPZ1CDw0Vn8P6uo1km /FGcNmoDyXwW6TmI+CyHgiYIItjSYPE6YpxQZtIiGxA79bZwvBO7QA/7CYPniu/i WyKiKLUOYnvKTqsr9hKOYvHGV74hjRb0EuycnEyw0SCtsoxWlrNnuP4CG22X9O0+ OvfD3jMAFSAmYooifK0CZyi+IFphFpTUmy+fq+hT6MAH9H3uQ88QWThrw+4hA5O0 rNPtwvL0WoK+4v8twQbOSRVd63J20oMGL7+nGnymnO5EA/XLVIlCSBFQhhNBKC3/ OeWlyP/v+n6KnWNY4Wo9daBgF6Vej0B/9E5Z46mOKIDO5Q9iIzG4bOh/iwv9C/7Q BCnbOYiXJyLZLOJ7k9AuE0DfeYzIZsNIyDwximc8wus937YE2/g= =Z/p4 -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.12-1 * Enable High Impedance pin configuration support for Intel pin control * Miscellaneous small improvements here and there The following is an automated git shortlog grouped by driver: baytrail: - Drop duplicate return statement intel: - Constify struct intel_pinctrl parameter - Inline intel_gpio_community_irq_handler() - Introduce for_each_intel_gpio_group() helper et al. - Constify intel_get_community() returned object - Implement high impedance support - Add __intel_gpio_get_direction() helper - Refactor __intel_gpio_set_direction() to be more useful - Move debounce validation out of the lock Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
commit
264c13114b
@ -560,9 +560,10 @@ static DEFINE_RAW_SPINLOCK(byt_lock);
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static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
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int reg)
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{
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struct intel_community *comm = intel_get_community(vg, offset);
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const struct intel_community *comm;
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u32 reg_offset;
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comm = intel_get_community(vg, offset);
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if (!comm)
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return NULL;
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@ -1541,10 +1542,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
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}
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ret = devm_gpiochip_add_data(vg->dev, gc, vg);
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if (ret) {
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if (ret)
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dev_err(vg->dev, "failed adding byt-gpio chip\n");
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return ret;
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}
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return ret;
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}
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@ -70,6 +70,12 @@
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#define PADCFG0_PMODE_SHIFT 10
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#define PADCFG0_PMODE_MASK GENMASK(13, 10)
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#define PADCFG0_PMODE_GPIO 0
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#define PADCFG0_GPIODIS_SHIFT 8
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#define PADCFG0_GPIODIS_MASK GENMASK(9, 8)
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#define PADCFG0_GPIODIS_NONE 0
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#define PADCFG0_GPIODIS_OUTPUT 1
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#define PADCFG0_GPIODIS_INPUT 2
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#define PADCFG0_GPIODIS_FULL 3
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#define PADCFG0_GPIORXDIS BIT(9)
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#define PADCFG0_GPIOTXDIS BIT(8)
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#define PADCFG0_GPIORXSTATE BIT(1)
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@ -108,13 +114,30 @@ struct intel_community_context {
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#define pin_to_padno(c, p) ((p) - (c)->pin_base)
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#define padgroup_offset(g, p) ((p) - (g)->base)
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struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin)
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{
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struct intel_community *community;
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int i;
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#define for_each_intel_pin_community(pctrl, community) \
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for (unsigned int __ci = 0; \
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__ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \
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__ci++) \
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for (i = 0; i < pctrl->ncommunities; i++) {
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community = &pctrl->communities[i];
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#define for_each_intel_community_pad_group(community, grp) \
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for (unsigned int __gi = 0; \
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__gi < community->ngpps && (grp = &community->gpps[__gi]); \
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__gi++) \
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#define for_each_intel_pad_group(pctrl, community, grp) \
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for_each_intel_pin_community(pctrl, community) \
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for_each_intel_community_pad_group(community, grp)
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#define for_each_intel_gpio_group(pctrl, community, grp) \
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for_each_intel_pad_group(pctrl, community, grp) \
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if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else
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const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
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unsigned int pin)
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{
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const struct intel_community *community;
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for_each_intel_pin_community(pctrl, community) {
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if (pin >= community->pin_base &&
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pin < community->pin_base + community->npins)
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return community;
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@ -129,11 +152,9 @@ static const struct intel_padgroup *
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intel_community_get_padgroup(const struct intel_community *community,
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unsigned int pin)
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{
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int i;
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for (i = 0; i < community->ngpps; i++) {
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const struct intel_padgroup *padgrp = &community->gpps[i];
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const struct intel_padgroup *padgrp;
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for_each_intel_community_pad_group(community, padgrp) {
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if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
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return padgrp;
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}
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@ -161,7 +182,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
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return community->pad_regs + reg + padno * nregs * 4;
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}
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static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
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static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin)
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{
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const struct intel_community *community;
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const struct intel_padgroup *padgrp;
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@ -186,7 +207,7 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pi
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return !(readl(padown) & PADOWN_MASK(gpp_offset));
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}
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static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
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static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin)
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{
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const struct intel_community *community;
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const struct intel_padgroup *padgrp;
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@ -212,7 +233,6 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
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/**
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* enum - Locking variants of the pad configuration
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*
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* @PAD_UNLOCKED: pad is fully controlled by the configuration registers
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* @PAD_LOCKED: pad configuration registers, except TX state, are locked
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* @PAD_LOCKED_TX: pad configuration TX state is locked
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@ -229,9 +249,9 @@ enum {
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PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
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};
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static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
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static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin)
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{
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struct intel_community *community;
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const struct intel_community *community;
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const struct intel_padgroup *padgrp;
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unsigned int offset, gpp_offset;
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u32 value;
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@ -267,19 +287,19 @@ static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
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return ret;
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}
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static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
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static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin)
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{
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return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
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}
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static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
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static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin)
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{
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return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
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}
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int intel_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->ngroups;
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}
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@ -287,7 +307,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL);
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const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->groups[group].grp.name;
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}
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@ -296,7 +316,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL);
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int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
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const unsigned int **pins, unsigned int *npins)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*pins = pctrl->soc->groups[group].grp.pins;
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*npins = pctrl->soc->groups[group].grp.npins;
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@ -364,7 +384,7 @@ static const struct pinctrl_ops intel_pinctrl_ops = {
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int intel_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->nfunctions;
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}
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@ -372,7 +392,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL);
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const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->functions[function].func.name;
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}
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@ -381,7 +401,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL);
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int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
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const char * const **groups, unsigned int * const ngroups)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctrl->soc->functions[function].func.groups;
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*ngroups = pctrl->soc->functions[function].func.ngroups;
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@ -429,19 +449,49 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
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return 0;
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}
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static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
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{
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u32 value;
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/**
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* enum - Possible pad physical connections
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* @PAD_CONNECT_NONE: pad is fully disconnected
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* @PAD_CONNECT_INPUT: pad is in input only mode
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* @PAD_CONNECT_OUTPUT: pad is in output only mode
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* @PAD_CONNECT_FULL: pad is fully connected
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*/
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enum {
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PAD_CONNECT_NONE = 0,
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PAD_CONNECT_INPUT = 1,
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PAD_CONNECT_OUTPUT = 2,
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PAD_CONNECT_FULL = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT,
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};
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value = readl(padcfg0);
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if (input) {
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static int __intel_gpio_get_direction(u32 value)
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{
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switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) {
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case PADCFG0_GPIODIS_FULL:
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return PAD_CONNECT_NONE;
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case PADCFG0_GPIODIS_OUTPUT:
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return PAD_CONNECT_INPUT;
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case PADCFG0_GPIODIS_INPUT:
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return PAD_CONNECT_OUTPUT;
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case PADCFG0_GPIODIS_NONE:
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return PAD_CONNECT_FULL;
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default:
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return -ENOTSUPP;
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};
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}
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static u32 __intel_gpio_set_direction(u32 value, bool input, bool output)
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{
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if (input)
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value &= ~PADCFG0_GPIORXDIS;
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value |= PADCFG0_GPIOTXDIS;
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} else {
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value &= ~PADCFG0_GPIOTXDIS;
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else
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value |= PADCFG0_GPIORXDIS;
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}
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writel(value, padcfg0);
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if (output)
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value &= ~PADCFG0_GPIOTXDIS;
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else
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value |= PADCFG0_GPIOTXDIS;
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return value;
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}
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static int __intel_gpio_get_gpio_mode(u32 value)
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@ -465,8 +515,7 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
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value |= PADCFG0_PMODE_GPIO;
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/* Disable TX buffer and enable RX (this will be input) */
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value &= ~PADCFG0_GPIORXDIS;
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value |= PADCFG0_GPIOTXDIS;
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value = __intel_gpio_set_direction(value, true, false);
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/* Disable SCI/SMI/NMI generation */
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value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
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@ -512,12 +561,18 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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void __iomem *padcfg0;
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u32 value;
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padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
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guard(raw_spinlock_irqsave)(&pctrl->lock);
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__intel_gpio_set_direction(padcfg0, input);
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value = readl(padcfg0);
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if (input)
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value = __intel_gpio_set_direction(value, true, false);
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else
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value = __intel_gpio_set_direction(value, false, true);
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writel(value, padcfg0);
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return 0;
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}
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@ -612,6 +667,23 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
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return 0;
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}
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static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin,
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enum pin_config_param param, u32 *arg)
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{
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void __iomem *padcfg0;
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u32 value;
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padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
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scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
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value = readl(padcfg0);
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if (__intel_gpio_get_direction(value) != PAD_CONNECT_NONE)
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return -EINVAL;
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return 0;
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}
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static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
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enum pin_config_param param, u32 *arg)
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{
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@ -655,6 +727,12 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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return ret;
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break;
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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ret = intel_config_get_high_impedance(pctrl, pin, param, &arg);
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if (ret)
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return ret;
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break;
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case PIN_CONFIG_INPUT_DEBOUNCE:
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ret = intel_config_get_debounce(pctrl, pin, param, &arg);
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if (ret)
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@ -753,11 +831,34 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
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return 0;
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}
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static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin)
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{
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void __iomem *padcfg0;
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u32 value;
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padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
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guard(raw_spinlock_irqsave)(&pctrl->lock);
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value = readl(padcfg0);
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value = __intel_gpio_set_direction(value, false, false);
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writel(value, padcfg0);
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}
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static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
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unsigned int pin, unsigned int debounce)
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{
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void __iomem *padcfg0, *padcfg2;
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u32 value0, value2;
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unsigned long v;
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if (debounce) {
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v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
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if (v < 3 || v > 15)
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return -EINVAL;
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} else {
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v = 0;
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}
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padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
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if (!padcfg2)
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@ -770,21 +871,15 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
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value0 = readl(padcfg0);
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value2 = readl(padcfg2);
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/* Disable glitch filter and debouncer */
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value0 &= ~PADCFG0_PREGFRXSEL;
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value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
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if (debounce) {
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unsigned long v;
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v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
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if (v < 3 || v > 15)
|
||||
return -EINVAL;
|
||||
|
||||
value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT);
|
||||
if (v) {
|
||||
/* Enable glitch filter and debouncer */
|
||||
value0 |= PADCFG0_PREGFRXSEL;
|
||||
value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
|
||||
value2 |= PADCFG2_DEBEN;
|
||||
} else {
|
||||
/* Disable glitch filter and debouncer */
|
||||
value0 &= ~PADCFG0_PREGFRXSEL;
|
||||
value2 &= ~PADCFG2_DEBEN;
|
||||
}
|
||||
|
||||
writel(value0, padcfg0);
|
||||
@ -812,6 +907,10 @@ static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
return ret;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
|
||||
intel_gpio_set_high_impedance(pctrl, pin);
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_INPUT_DEBOUNCE:
|
||||
ret = intel_config_set_debounce(pctrl, pin,
|
||||
pinconf_to_config_argument(configs[i]));
|
||||
@ -854,34 +953,21 @@ static const struct pinctrl_desc intel_pinctrl_desc = {
|
||||
* Return: a pin number and pointers to the community and pad group, which
|
||||
* the pin belongs to, or negative error code if translation can't be done.
|
||||
*/
|
||||
static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
|
||||
static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset,
|
||||
const struct intel_community **community,
|
||||
const struct intel_padgroup **padgrp)
|
||||
{
|
||||
int i;
|
||||
const struct intel_community *comm;
|
||||
const struct intel_padgroup *grp;
|
||||
|
||||
for (i = 0; i < pctrl->ncommunities; i++) {
|
||||
const struct intel_community *comm = &pctrl->communities[i];
|
||||
int j;
|
||||
for_each_intel_gpio_group(pctrl, comm, grp) {
|
||||
if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) {
|
||||
if (community)
|
||||
*community = comm;
|
||||
if (padgrp)
|
||||
*padgrp = grp;
|
||||
|
||||
for (j = 0; j < comm->ngpps; j++) {
|
||||
const struct intel_padgroup *pgrp = &comm->gpps[j];
|
||||
|
||||
if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
|
||||
continue;
|
||||
|
||||
if (offset >= pgrp->gpio_base &&
|
||||
offset < pgrp->gpio_base + pgrp->size) {
|
||||
int pin;
|
||||
|
||||
pin = pgrp->base + offset - pgrp->gpio_base;
|
||||
if (community)
|
||||
*community = comm;
|
||||
if (padgrp)
|
||||
*padgrp = pgrp;
|
||||
|
||||
return pin;
|
||||
}
|
||||
return grp->base + offset - grp->gpio_base;
|
||||
}
|
||||
}
|
||||
|
||||
@ -897,7 +983,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
|
||||
*
|
||||
* Return: a GPIO offset, or negative error code if translation can't be done.
|
||||
*/
|
||||
static int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
|
||||
static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin)
|
||||
{
|
||||
const struct intel_community *community;
|
||||
const struct intel_padgroup *padgrp;
|
||||
@ -929,7 +1015,7 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
return -EINVAL;
|
||||
|
||||
padcfg0 = readl(reg);
|
||||
if (!(padcfg0 & PADCFG0_GPIOTXDIS))
|
||||
if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
|
||||
return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
|
||||
|
||||
return !!(padcfg0 & PADCFG0_GPIORXSTATE);
|
||||
@ -982,10 +1068,10 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
if (padcfg0 & PADCFG0_PMODE_MASK)
|
||||
return -EINVAL;
|
||||
|
||||
if (padcfg0 & PADCFG0_GPIOTXDIS)
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
|
||||
@ -1171,15 +1257,16 @@ static const struct irq_chip intel_gpio_irq_chip = {
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
|
||||
const struct intel_community *community)
|
||||
static irqreturn_t intel_gpio_irq(int irq, void *data)
|
||||
{
|
||||
struct gpio_chip *gc = &pctrl->chip;
|
||||
unsigned int gpp;
|
||||
const struct intel_community *community;
|
||||
const struct intel_padgroup *padgrp;
|
||||
struct intel_pinctrl *pctrl = data;
|
||||
int ret = 0;
|
||||
|
||||
for (gpp = 0; gpp < community->ngpps; gpp++) {
|
||||
const struct intel_padgroup *padgrp = &community->gpps[gpp];
|
||||
/* Need to check all communities for pending interrupts */
|
||||
for_each_intel_pad_group(pctrl, community, padgrp) {
|
||||
struct gpio_chip *gc = &pctrl->chip;
|
||||
unsigned long pending, enabled;
|
||||
unsigned int gpp, gpp_offset;
|
||||
void __iomem *reg, *is;
|
||||
@ -1203,36 +1290,17 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
|
||||
ret += pending ? 1 : 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static irqreturn_t intel_gpio_irq(int irq, void *data)
|
||||
{
|
||||
const struct intel_community *community;
|
||||
struct intel_pinctrl *pctrl = data;
|
||||
unsigned int i;
|
||||
int ret = 0;
|
||||
|
||||
/* Need to check all communities for pending interrupts */
|
||||
for (i = 0; i < pctrl->ncommunities; i++) {
|
||||
community = &pctrl->communities[i];
|
||||
ret += intel_gpio_community_irq_handler(pctrl, community);
|
||||
}
|
||||
|
||||
return IRQ_RETVAL(ret);
|
||||
}
|
||||
|
||||
static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
|
||||
{
|
||||
int i;
|
||||
const struct intel_community *community;
|
||||
|
||||
for (i = 0; i < pctrl->ncommunities; i++) {
|
||||
const struct intel_community *community;
|
||||
for_each_intel_pin_community(pctrl, community) {
|
||||
void __iomem *reg, *is;
|
||||
unsigned int gpp;
|
||||
|
||||
community = &pctrl->communities[i];
|
||||
|
||||
for (gpp = 0; gpp < community->ngpps; gpp++) {
|
||||
reg = community->regs + community->ie_offset + gpp * 4;
|
||||
is = community->regs + community->is_offset + gpp * 4;
|
||||
@ -1257,36 +1325,17 @@ static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
|
||||
const struct intel_community *community)
|
||||
{
|
||||
int ret = 0, i;
|
||||
|
||||
for (i = 0; i < community->ngpps; i++) {
|
||||
const struct intel_padgroup *gpp = &community->gpps[i];
|
||||
|
||||
if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
|
||||
continue;
|
||||
|
||||
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
|
||||
gpp->gpio_base, gpp->base,
|
||||
gpp->size);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
|
||||
{
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
int ret, i;
|
||||
const struct intel_community *community;
|
||||
const struct intel_padgroup *grp;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < pctrl->ncommunities; i++) {
|
||||
struct intel_community *community = &pctrl->communities[i];
|
||||
|
||||
ret = intel_gpio_add_community_ranges(pctrl, community);
|
||||
for_each_intel_gpio_group(pctrl, community, grp) {
|
||||
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
|
||||
grp->gpio_base, grp->base,
|
||||
grp->size);
|
||||
if (ret) {
|
||||
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
|
||||
return ret;
|
||||
@ -1299,20 +1348,12 @@ static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
|
||||
static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
|
||||
{
|
||||
const struct intel_community *community;
|
||||
const struct intel_padgroup *grp;
|
||||
unsigned int ngpio = 0;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < pctrl->ncommunities; i++) {
|
||||
community = &pctrl->communities[i];
|
||||
for (j = 0; j < community->ngpps; j++) {
|
||||
const struct intel_padgroup *gpp = &community->gpps[j];
|
||||
|
||||
if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
|
||||
continue;
|
||||
|
||||
if (gpp->gpio_base + gpp->size > ngpio)
|
||||
ngpio = gpp->gpio_base + gpp->size;
|
||||
}
|
||||
for_each_intel_gpio_group(pctrl, community, grp) {
|
||||
if (grp->gpio_base + grp->size > ngpio)
|
||||
ngpio = grp->gpio_base + grp->size;
|
||||
}
|
||||
|
||||
return ngpio;
|
||||
@ -1682,7 +1723,8 @@ EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL);
|
||||
|
||||
static bool __intel_gpio_is_direct_irq(u32 value)
|
||||
{
|
||||
return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
|
||||
return (value & PADCFG0_GPIROUTIOXAPIC) &&
|
||||
(__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) &&
|
||||
(__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
|
||||
}
|
||||
|
||||
|
||||
@ -264,7 +264,8 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
|
||||
|
||||
extern const struct dev_pm_ops intel_pinctrl_pm_ops;
|
||||
|
||||
struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin);
|
||||
const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
|
||||
unsigned int pin);
|
||||
|
||||
int intel_get_groups_count(struct pinctrl_dev *pctldev);
|
||||
const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);
|
||||
|
||||
@ -211,7 +211,7 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
|
||||
int reg)
|
||||
{
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(chip);
|
||||
struct intel_community *comm;
|
||||
const struct intel_community *comm;
|
||||
int reg_offset;
|
||||
|
||||
comm = intel_get_community(lg, offset);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user