spmi: pmic-arb: Add support for PMIC v7
PMIC v7 has different offset values and seqeunces, so add support for this new version of PMIC Signed-off-by: David Collins <collinsd@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 HDK Acked-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221110100755.4032505-3-vkoul@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
David Collins
Greg Kroah-Hartman
parent
2d2879e183
commit
231601cd22
@ -22,8 +22,14 @@
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#define PMIC_ARB_VERSION_V2_MIN 0x20010000
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#define PMIC_ARB_VERSION_V3_MIN 0x30000000
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#define PMIC_ARB_VERSION_V5_MIN 0x50000000
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#define PMIC_ARB_VERSION_V7_MIN 0x70000000
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#define PMIC_ARB_INT_EN 0x0004
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#define PMIC_ARB_FEATURES 0x0004
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#define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)
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#define PMIC_ARB_FEATURES1 0x0008
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/* PMIC Arbiter channel registers offsets */
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#define PMIC_ARB_CMD 0x00
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#define PMIC_ARB_CONFIG 0x04
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@ -48,7 +54,6 @@
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#define INVALID_EE 0xFF
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/* Ownership Table */
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#define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
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#define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
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/* Channel Status fields */
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@ -91,6 +96,7 @@ enum pmic_arb_channel {
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/* Maximum number of support PMIC peripherals */
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#define PMIC_ARB_MAX_PERIPHS 512
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#define PMIC_ARB_MAX_PERIPHS_V7 1024
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#define PMIC_ARB_TIMEOUT_US 1000
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#define PMIC_ARB_MAX_TRANS_BYTES (8)
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@ -104,12 +110,12 @@ enum pmic_arb_channel {
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((((slave_id) & 0xF) << 28) | \
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(((periph_id) & 0xFF) << 20) | \
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(((irq_id) & 0x7) << 16) | \
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(((apid) & 0x1FF) << 0))
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(((apid) & 0x3FF) << 0))
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#define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
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#define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
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#define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
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#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x1FF)
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#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)
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struct pmic_arb_ver_ops;
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@ -130,13 +136,21 @@ struct apid_data {
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* @channel: execution environment channel to use for accesses.
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* @irq: PMIC ARB interrupt.
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* @ee: the current Execution Environment
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* @bus_instance: on v7: 0 = primary SPMI bus, 1 = secondary SPMI bus
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* @min_apid: minimum APID (used for bounding IRQ search)
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* @max_apid: maximum APID
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* @base_apid: on v7: minimum APID associated with the particular SPMI
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* bus instance
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* @apid_count: on v5 and v7: number of APIDs associated with the
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* particular SPMI bus instance
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* @mapping_table: in-memory copy of PPID -> APID mapping table.
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* @domain: irq domain object for PMIC IRQ domain
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* @spmic: SPMI controller object
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* @ver_ops: version dependent operations.
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* @ppid_to_apid in-memory copy of PPID -> APID mapping table.
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* @ppid_to_apid: in-memory copy of PPID -> APID mapping table.
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* @last_apid: Highest value APID in use
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* @apid_data: Table of data for all APIDs
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* @max_periphs: Number of elements in apid_data[]
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*/
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struct spmi_pmic_arb {
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void __iomem *rd_base;
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@ -149,8 +163,11 @@ struct spmi_pmic_arb {
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u8 channel;
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int irq;
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u8 ee;
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u32 bus_instance;
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u16 min_apid;
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u16 max_apid;
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u16 base_apid;
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int apid_count;
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u32 *mapping_table;
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DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
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struct irq_domain *domain;
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@ -158,7 +175,8 @@ struct spmi_pmic_arb {
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const struct pmic_arb_ver_ops *ver_ops;
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u16 *ppid_to_apid;
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u16 last_apid;
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struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS];
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struct apid_data *apid_data;
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int max_periphs;
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};
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/**
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@ -180,6 +198,7 @@ struct spmi_pmic_arb {
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* @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
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* on v2 address of SPMI_PIC_IRQ_CLEARn.
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* @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
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* @apid_owner: on v2 and later address of SPMI_PERIPHn_2OWNER_TABLE_REG
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*/
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struct pmic_arb_ver_ops {
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const char *ver_str;
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@ -196,6 +215,7 @@ struct pmic_arb_ver_ops {
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void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
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void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
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u32 (*apid_map_offset)(u16 n);
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void __iomem *(*apid_owner)(struct spmi_pmic_arb *pmic_arb, u16 n);
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};
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static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
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@ -627,6 +647,11 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
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struct irq_chip *chip = irq_desc_get_chip(desc);
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int first = pmic_arb->min_apid;
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int last = pmic_arb->max_apid;
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/*
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* acc_offset will be non-zero for the secondary SPMI bus instance on
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* v7 controllers.
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*/
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int acc_offset = pmic_arb->base_apid >> 5;
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u8 ee = pmic_arb->ee;
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u32 status, enable, handled = 0;
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int i, id, apid;
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@ -637,8 +662,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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for (i = first >> 5; i <= last >> 5; ++i) {
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status = readl_relaxed(
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ver_ops->owner_acc_status(pmic_arb, ee, i));
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status = readl_relaxed(ver_ops->owner_acc_status(pmic_arb, ee, i - acc_offset));
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if (status)
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acc_valid = true;
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@ -983,8 +1007,8 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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if (offset >= pmic_arb->core_size)
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break;
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regval = readl_relaxed(pmic_arb->cnfg +
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SPMI_OWNERSHIP_TABLE_REG(apid));
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regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
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apid));
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apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
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apidd->write_ee = apidd->irq_ee;
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@ -1020,21 +1044,30 @@ static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
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{
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struct apid_data *apidd = pmic_arb->apid_data;
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struct apid_data *apidd;
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struct apid_data *prev_apidd;
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u16 i, apid, ppid;
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u16 i, apid, ppid, apid_max;
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bool valid, is_irq_ee;
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u32 regval, offset;
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/*
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* In order to allow multiple EEs to write to a single PPID in arbiter
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* version 5, there is more than one APID mapped to each PPID.
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* version 5 and 7, there is more than one APID mapped to each PPID.
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* The owner field for each of these mappings specifies the EE which is
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* allowed to write to the APID. The owner of the last (highest) APID
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* which has the IRQ owner bit set for a given PPID will receive
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* interrupts from the PPID.
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*
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* In arbiter version 7, the APID numbering space is divided between
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* the primary bus (0) and secondary bus (1) such that:
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* APID = 0 to N-1 are assigned to the primary bus
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* APID = N to N+M-1 are assigned to the secondary bus
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* where N = number of APIDs supported by the primary bus and
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* M = number of APIDs supported by the secondary bus
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*/
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for (i = 0; ; i++, apidd++) {
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apidd = &pmic_arb->apid_data[pmic_arb->base_apid];
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apid_max = pmic_arb->base_apid + pmic_arb->apid_count;
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for (i = pmic_arb->base_apid; i < apid_max; i++, apidd++) {
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offset = pmic_arb->ver_ops->apid_map_offset(i);
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if (offset >= pmic_arb->core_size)
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break;
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@ -1045,8 +1078,8 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
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ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
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is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
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regval = readl_relaxed(pmic_arb->cnfg +
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SPMI_OWNERSHIP_TABLE_REG(i));
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regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
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i));
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apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
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apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
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@ -1145,6 +1178,40 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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return offset;
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}
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/*
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* v7 offset per ee and per apid for observer channels and per apid for
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* read/write channels.
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*/
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static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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enum pmic_arb_channel ch_type)
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{
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u16 apid;
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int rc;
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u32 offset = 0;
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u16 ppid = (sid << 8) | (addr >> 8);
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rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
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if (rc < 0)
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return rc;
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apid = rc;
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switch (ch_type) {
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case PMIC_ARB_CHANNEL_OBS:
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offset = 0x8000 * pmic_arb->ee + 0x20 * apid;
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break;
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case PMIC_ARB_CHANNEL_RW:
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if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
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dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
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sid, addr);
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return -EPERM;
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}
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offset = 0x1000 * apid;
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break;
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}
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return offset;
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}
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static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
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{
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return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
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@ -1179,6 +1246,12 @@ pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
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return pmic_arb->intr + 0x10000 * m + 0x4 * n;
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}
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static void __iomem *
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pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
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{
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return pmic_arb->intr + 0x1000 * m + 0x4 * n;
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}
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static void __iomem *
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pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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@ -1197,6 +1270,12 @@ pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
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return pmic_arb->wr_base + 0x100 + 0x10000 * n;
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}
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static void __iomem *
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pmic_arb_acc_enable_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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return pmic_arb->wr_base + 0x100 + 0x1000 * n;
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}
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static void __iomem *
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pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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@ -1215,6 +1294,12 @@ pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
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return pmic_arb->wr_base + 0x104 + 0x10000 * n;
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}
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static void __iomem *
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pmic_arb_irq_status_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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return pmic_arb->wr_base + 0x104 + 0x1000 * n;
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}
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static void __iomem *
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pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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@ -1233,6 +1318,12 @@ pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
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return pmic_arb->wr_base + 0x108 + 0x10000 * n;
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}
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static void __iomem *
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pmic_arb_irq_clear_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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return pmic_arb->wr_base + 0x108 + 0x1000 * n;
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}
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static u32 pmic_arb_apid_map_offset_v2(u16 n)
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{
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return 0x800 + 0x4 * n;
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@ -1243,6 +1334,28 @@ static u32 pmic_arb_apid_map_offset_v5(u16 n)
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return 0x900 + 0x4 * n;
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}
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static u32 pmic_arb_apid_map_offset_v7(u16 n)
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{
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return 0x2000 + 0x4 * n;
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}
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static void __iomem *
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pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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return pmic_arb->cnfg + 0x700 + 0x4 * n;
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}
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/*
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* For arbiter version 7, APID ownership table registers have independent
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* numbering space for each SPMI bus instance, so each is indexed starting from
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* 0.
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*/
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static void __iomem *
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pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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return pmic_arb->cnfg + 0x4 * (n - pmic_arb->base_apid);
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}
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static const struct pmic_arb_ver_ops pmic_arb_v1 = {
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.ver_str = "v1",
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.ppid_to_apid = pmic_arb_ppid_to_apid_v1,
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@ -1254,6 +1367,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 = {
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.irq_status = pmic_arb_irq_status_v1,
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.irq_clear = pmic_arb_irq_clear_v1,
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.apid_map_offset = pmic_arb_apid_map_offset_v2,
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.apid_owner = pmic_arb_apid_owner_v2,
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};
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static const struct pmic_arb_ver_ops pmic_arb_v2 = {
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@ -1267,6 +1381,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 = {
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.irq_status = pmic_arb_irq_status_v2,
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.irq_clear = pmic_arb_irq_clear_v2,
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.apid_map_offset = pmic_arb_apid_map_offset_v2,
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.apid_owner = pmic_arb_apid_owner_v2,
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};
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static const struct pmic_arb_ver_ops pmic_arb_v3 = {
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@ -1280,6 +1395,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 = {
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.irq_status = pmic_arb_irq_status_v2,
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.irq_clear = pmic_arb_irq_clear_v2,
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.apid_map_offset = pmic_arb_apid_map_offset_v2,
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.apid_owner = pmic_arb_apid_owner_v2,
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};
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static const struct pmic_arb_ver_ops pmic_arb_v5 = {
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@ -1293,6 +1409,21 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 = {
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.irq_status = pmic_arb_irq_status_v5,
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.irq_clear = pmic_arb_irq_clear_v5,
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.apid_map_offset = pmic_arb_apid_map_offset_v5,
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.apid_owner = pmic_arb_apid_owner_v2,
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};
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static const struct pmic_arb_ver_ops pmic_arb_v7 = {
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.ver_str = "v7",
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.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
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.non_data_cmd = pmic_arb_non_data_cmd_v2,
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.offset = pmic_arb_offset_v7,
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.fmt_cmd = pmic_arb_fmt_cmd_v2,
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.owner_acc_status = pmic_arb_owner_acc_status_v7,
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.acc_enable = pmic_arb_acc_enable_v7,
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.irq_status = pmic_arb_irq_status_v7,
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.irq_clear = pmic_arb_irq_clear_v7,
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.apid_map_offset = pmic_arb_apid_map_offset_v7,
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.apid_owner = pmic_arb_apid_owner_v7,
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};
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static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
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@ -1319,8 +1450,18 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
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pmic_arb = spmi_controller_get_drvdata(ctrl);
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pmic_arb->spmic = ctrl;
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/*
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* Please don't replace this with devm_platform_ioremap_resource() or
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* devm_ioremap_resource(). These both result in a call to
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* devm_request_mem_region() which prevents multiple mappings of this
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* register address range. SoCs with PMIC arbiter v7 may define two
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* arbiter devices, for the two physical SPMI interfaces, which share
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* some register address ranges (i.e. "core", "obsrvr", and "chnls").
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* Ensure that both devices probe successfully by calling devm_ioremap()
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* which does not result in a devm_request_mem_region() call.
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*/
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
|
||||
core = devm_ioremap_resource(&ctrl->dev, res);
|
||||
core = devm_ioremap(&ctrl->dev, res->start, resource_size(res));
|
||||
if (IS_ERR(core)) {
|
||||
err = PTR_ERR(core);
|
||||
goto err_put_ctrl;
|
||||
@ -1349,12 +1490,15 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
pmic_arb->ver_ops = &pmic_arb_v2;
|
||||
else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v3;
|
||||
else
|
||||
else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v5;
|
||||
else
|
||||
pmic_arb->ver_ops = &pmic_arb_v7;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"obsrvr");
|
||||
pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
pmic_arb->rd_base = devm_ioremap(&ctrl->dev, res->start,
|
||||
resource_size(res));
|
||||
if (IS_ERR(pmic_arb->rd_base)) {
|
||||
err = PTR_ERR(pmic_arb->rd_base);
|
||||
goto err_put_ctrl;
|
||||
@ -1362,13 +1506,69 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"chnls");
|
||||
pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
pmic_arb->wr_base = devm_ioremap(&ctrl->dev, res->start,
|
||||
resource_size(res));
|
||||
if (IS_ERR(pmic_arb->wr_base)) {
|
||||
err = PTR_ERR(pmic_arb->wr_base);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
}
|
||||
|
||||
pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
|
||||
|
||||
if (hw_ver >= PMIC_ARB_VERSION_V7_MIN) {
|
||||
pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;
|
||||
/* Optional property for v7: */
|
||||
of_property_read_u32(pdev->dev.of_node, "qcom,bus-id",
|
||||
&pmic_arb->bus_instance);
|
||||
if (pmic_arb->bus_instance > 1) {
|
||||
err = -EINVAL;
|
||||
dev_err(&pdev->dev, "invalid bus instance (%u) specified\n",
|
||||
pmic_arb->bus_instance);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
if (pmic_arb->bus_instance == 0) {
|
||||
pmic_arb->base_apid = 0;
|
||||
pmic_arb->apid_count =
|
||||
readl_relaxed(core + PMIC_ARB_FEATURES) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
} else {
|
||||
pmic_arb->base_apid =
|
||||
readl_relaxed(core + PMIC_ARB_FEATURES) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
pmic_arb->apid_count =
|
||||
readl_relaxed(core + PMIC_ARB_FEATURES1) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
}
|
||||
|
||||
if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) {
|
||||
err = -EINVAL;
|
||||
dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
|
||||
pmic_arb->base_apid + pmic_arb->apid_count);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
} else if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
|
||||
pmic_arb->base_apid = 0;
|
||||
pmic_arb->apid_count = readl_relaxed(core + PMIC_ARB_FEATURES) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
|
||||
if (pmic_arb->apid_count > pmic_arb->max_periphs) {
|
||||
err = -EINVAL;
|
||||
dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
|
||||
pmic_arb->apid_count);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
}
|
||||
|
||||
pmic_arb->apid_data = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
|
||||
sizeof(*pmic_arb->apid_data),
|
||||
GFP_KERNEL);
|
||||
if (!pmic_arb->apid_data) {
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
|
||||
pmic_arb->ver_ops->ver_str, hw_ver);
|
||||
|
||||
@ -1420,7 +1620,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
pmic_arb->ee = ee;
|
||||
mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
|
||||
mapping_table = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
|
||||
sizeof(*mapping_table), GFP_KERNEL);
|
||||
if (!mapping_table) {
|
||||
err = -ENOMEM;
|
||||
@ -1431,7 +1631,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
/* Initialize max_apid/min_apid to the opposite bounds, during
|
||||
* the irq domain translation, we are sure to update these */
|
||||
pmic_arb->max_apid = 0;
|
||||
pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
|
||||
pmic_arb->min_apid = pmic_arb->max_periphs - 1;
|
||||
|
||||
platform_set_drvdata(pdev, ctrl);
|
||||
raw_spin_lock_init(&pmic_arb->lock);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user