powerpc fixes for 6.5 #2
- Fix PCIe MEM size for pci2 node on Turris 1.x boards. - Two minor build fixes. Thanks to: Christophe Leroy, Douglas Anderson, Pali Rohár, Petr Mladek, Randy Dunlap. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEJFGtCPCthwEv2Y/bUevqPMjhpYAFAmSoB1MTHG1wZUBlbGxl cm1hbi5pZC5hdQAKCRBR6+o8yOGlgPvMEACrkNuqV1mpI2c6m41mWZDBt/9YmSBX Gh061wI5KN4X2hGNvVJAFs49zuWl2SAET3UQxxk4Bux5HsIoZsdqFDZaTCT17zNo 8kFPajqwEbLQ1JgrFH3Y9ZMXYhR09l3jJ+lkf1JBvP4CQGfrxf2vRPu9+qGsnEeQ +9d9Zy3GWXCqhRTcDAocLsY0f+Ra5DHC2t7tynoXDy4SR0G5/HOfNgg3Ye3juu6u NHXI2w3KZfRaRXjq/V35HAxODOnso7UlIImsnk6a4GRV+VkYbBcoRTlbHJiPf4f+ DaPx38C8Sn0SM90HT4ck+jc8OLm2RGpcmPnBSHvv6EvGC1CysLMvVaw7ZFmpdYlN e9A9KYea+WkMOnb9J+xsLUN3sYBfflGBOSiRTpOKBQCaH2bNiT7d7Gz1FoRj6l0Q zTjoQEBPo/RbpdZl4ZHXj4QUxZzQSkituqhVgK8675IwYR65cekM1SMnVGgMdA7o BHczjvGC9I9c/yletazqQuQWR+Kn9WXiwZ3Aeh0uKIBgjXSId5n4GTToj68/pUtj XN8kvZYrb8W3br/7XbGmp7+55NJq2l9nqOcQPMX17z2jVRRK+gtP2MBGWu7XbUoL CBQXpke7dHtf75TxA2WmbWn2Jy+0EO1U43kEBv1+GCS9IfoyDX4pobw1QXHgH5Gl r1VbqtrcTcvTrQ== =YCPm -----END PGP SIGNATURE----- Merge tag 'powerpc-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: - Fix PCIe MEM size for pci2 node on Turris 1.x boards - Two minor build fixes Thanks to Christophe Leroy, Douglas Anderson, Pali Rohár, Petr Mladek, and Randy Dunlap. * tag 'powerpc-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc: dts: turris1x.dts: Fix PCIe MEM size for pci2 node powerpc: Include asm/nmi.c in mobility.c for watchdog_hardlockup_set_timeout_pct() powerpc: allow PPC_EARLY_DEBUG_CPM only when SERIAL_CPM=y
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22dcc7d77f
@ -240,7 +240,7 @@ config PPC_EARLY_DEBUG_40x
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config PPC_EARLY_DEBUG_CPM
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bool "Early serial debugging for Freescale CPM-based serial ports"
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depends on SERIAL_CPM
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depends on SERIAL_CPM=y
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help
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Select this to enable early debugging for Freescale chips
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using a CPM-based serial port. This assumes that the bootwrapper
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@ -476,12 +476,12 @@
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* channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
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* slot 1 (CN5), channels 2 and 3 to connector P600.
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*
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* P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller
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* P2020 PCIe Root Port does not use PCIe MEM and xHCI controller
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* uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
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* So allocate 2MB of PCIe MEM for this PCIe bus.
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* So allocate 128kB of PCIe MEM for this PCIe bus.
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*/
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reg = <0 0xffe08000 0 0x1000>;
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ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */
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ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00020000>, /* MEM */
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<0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
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pcie@0 {
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@ -24,6 +24,7 @@
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#include <linux/stringify.h>
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#include <asm/machdep.h>
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#include <asm/nmi.h>
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#include <asm/rtas.h>
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#include "pseries.h"
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#include "vas.h" /* vas_migration_handler() */
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