Documentation/gpu: Add an explanation about the DC weekly patches
This commit introduces some explanation about the display team validation. Changes since V1: - Remove unprecise information about the DC process for now, can be added later on. - Jani: Fix bullets Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -7,18 +7,80 @@ drm/amd/display - Display Core (DC)
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AMD display engine is partially shared with other operating systems; for this
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reason, our Display Core Driver is divided into two pieces:
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1. **Display Core (DC)** contains the OS-agnostic components. Things like
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#. **Display Core (DC)** contains the OS-agnostic components. Things like
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hardware programming and resource management are handled here.
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2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
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amdgpu base driver and DRM are implemented here.
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#. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
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amdgpu base driver and DRM are implemented here. For example, you can check
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display/amdgpu_dm/ folder.
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------------------
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DC Code validation
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------------------
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Maintaining the same code base across multiple OSes requires a lot of
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synchronization effort between repositories and exhaustive validation. In the
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DC case, we maintain a tree to centralize code from different parts. The shared
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repository has integration tests with our Internal Linux CI farm, and we run a
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comprehensive set of IGT tests in various AMD GPUs/APUs (mostly recent dGPUs
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and APUs). Our CI also checks ARM64/32, PPC64/32, and x86_64/32 compilation
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with DCN enabled and disabled.
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When we upstream a new feature or some patches, we pack them in a patchset with
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the prefix **DC Patches for <DATE>**, which is created based on the latest
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`amd-staging-drm-next <https://gitlab.freedesktop.org/agd5f/linux>`_. All of
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those patches are under a DC version tested as follows:
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* Ensure that every patch compiles and the entire series pass our set of IGT
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test in different hardware.
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* Prepare a branch with those patches for our validation team. If there is an
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error, a developer will debug as fast as possible; usually, a simple bisect
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in the series is enough to point to a bad change, and two possible actions
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emerge: fix the issue or drop the patch. If it is not an easy fix, the bad
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patch is dropped.
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* Finally, developers wait a few days for community feedback before we merge
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the series.
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It is good to stress that the test phase is something that we take extremely
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seriously, and we never merge anything that fails our validation. Follows an
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overview of our test set:
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#. Manual test
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* Multiple Hotplugs with DP and HDMI.
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* Stress test with multiple display configuration changes via the user interface.
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* Validate VRR behaviour.
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* Check PSR.
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* Validate MPO when playing video.
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* Test more than two displays connected at the same time.
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* Check suspend/resume.
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* Validate FPO.
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* Check MST.
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#. Automated test
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* IGT tests in a farm with GPUs and APUs that support DCN and DCE.
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* Compilation validation with the latest GCC and Clang from LTS distro.
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* Cross-compilation for PowerPC 64/32, ARM 64/32, and x86 32.
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In terms of test setup for CI and manual tests, we usually use:
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#. The latest Ubuntu LTS.
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#. In terms of userspace, we only use fully updated open-source components
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provided by the distribution official package manager.
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#. Regarding IGT, we use the latest code from the upstream.
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#. Most of the manual tests are conducted in the GNome but we also use KDE.
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Notice that someone from our test team will always reply to the cover letter
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with the test report.
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--------------
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DC Information
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--------------
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The display pipe is responsible for "scanning out" a rendered frame from the
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GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In other words,
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it would:
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1. Read frame information from memory;
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2. Perform required transformation;
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3. Send pixel data to sink devices.
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#. Read frame information from memory;
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#. Perform required transformation;
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#. Send pixel data to sink devices.
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If you want to learn more about our driver details, take a look at the below
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table of content:
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@ -26,8 +88,8 @@ table of content:
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.. toctree::
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display-manager.rst
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dc-debug.rst
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dcn-overview.rst
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dcn-blocks.rst
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mpo-overview.rst
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dc-debug.rst
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dc-glossary.rst
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