1

One build fix for 32-bit arches using the Qualcomm PLL driver. It's

cheaper to use a comparison here instead of a division so we just do
 that to fix the build.
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmbjdk4RHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSUNjA/8CYfF/DgogiFcxG2QsG5jDIgFL027PFSN
 FuUZ1kwf0vIMeLT5Oq1baURltaEk4/PbAJEQvF8i5DTXy5sfFKiZzWc6yLFpVsB3
 2FynvH9CBYnSsdFYNn5lD3HNXPNmNuBA528jhTF/AGrES6cBE41kXtxIy0HsptRV
 Zdnh+aD6igygeLcTE3BHaalfHVC13nHm/YABKYGf9kWyCIYy3CxAnT+ODkG5f4R6
 kFWj+dJ3bGs7k2CroOvsVO6bpAaEnrQWu0uvPEL9cZRt8x/daH0ZbtvPHLlbr28H
 0vswkTfhTuj0jCgMY9P0VKkipT53ETVWCzTV8dz/aDuBqfsPMBtZH7I9T/JSlOG9
 ycUGnDfdpHM8yYNpDVXnoY4dgVj/S74eH2rVPpouTnkj3wW7d5OWQAGAObO/uazt
 204vLnXA1uJUbO1HyqloYZId/FF3+Blw7tP9IiMNDv3LFefMhxbURXrevG6RloUg
 BC4O9abauUazh2wJYtoRqpLdui0OAgjkEcdwn/NEzeo7Gchd+c3hNMfBLxYArwnT
 BYPdHXI4vNzqTKAkw6V6J3S3IpcYZWeS+psMxQesUmSqmzFUKt6A81ZXpgJAg6O1
 v7v8EO2iBTM64+Fcw5JAJP7LiHNw6iyNcMrB+grKsLEZMIhWod6Q/kTXnby3P9qz
 mCh2OcXsFjc=
 =ln0u
 -----END PGP SIGNATURE-----

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fix from Stephen Boyd:
 "One build fix for 32-bit arches using the Qualcomm PLL driver. It's
  cheaper to use a comparison here instead of a division so we just do
  that to fix the build"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val()
This commit is contained in:
Linus Torvalds 2024-09-12 16:32:32 -07:00
commit 196145c606

View File

@ -2124,10 +2124,8 @@ static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32
quotient = rate; quotient = rate;
remainder = do_div(quotient, prate); remainder = do_div(quotient, prate);
*l = quotient;
if ((remainder * 2) / prate) *l = rate + (u32)(remainder * 2 >= prate);
*l = *l + 1;
} }
static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,