dt-bindings: clk: meson8b-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every meson8b-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-11-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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@ -77,114 +77,6 @@
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#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
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#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
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/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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#define CLKID_MPLL0_DIV 96
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#define CLKID_MPLL1_DIV 97
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#define CLKID_MPLL2_DIV 98
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#define CLKID_CPU_IN_SEL 99
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#define CLKID_CPU_IN_DIV2 100
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#define CLKID_CPU_IN_DIV3 101
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#define CLKID_CPU_SCALE_DIV 102
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#define CLKID_CPU_SCALE_OUT_SEL 103
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#define CLKID_MPLL_PREDIV 104
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#define CLKID_FCLK_DIV2_DIV 105
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#define CLKID_FCLK_DIV3_DIV 106
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#define CLKID_FCLK_DIV4_DIV 107
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#define CLKID_FCLK_DIV5_DIV 108
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#define CLKID_FCLK_DIV7_DIV 109
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#define CLKID_NAND_SEL 110
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#define CLKID_NAND_DIV 111
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#define CLKID_PLL_FIXED_DCO 113
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#define CLKID_HDMI_PLL_DCO 114
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#define CLKID_PLL_SYS_DCO 115
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#define CLKID_CPU_CLK_DIV2 116
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#define CLKID_CPU_CLK_DIV3 117
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#define CLKID_CPU_CLK_DIV4 118
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#define CLKID_CPU_CLK_DIV5 119
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#define CLKID_CPU_CLK_DIV6 120
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#define CLKID_CPU_CLK_DIV7 121
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#define CLKID_CPU_CLK_DIV8 122
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#define CLKID_APB_SEL 123
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#define CLKID_PERIPH_SEL 125
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#define CLKID_AXI_SEL 127
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#define CLKID_L2_DRAM_SEL 129
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#define CLKID_HDMI_PLL_LVDS_OUT 131
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#define CLKID_VID_PLL_IN_SEL 133
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#define CLKID_VID_PLL_IN_EN 134
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#define CLKID_VID_PLL_PRE_DIV 135
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#define CLKID_VID_PLL_POST_DIV 136
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#define CLKID_VCLK_IN_EN 139
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#define CLKID_VCLK_DIV1 140
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#define CLKID_VCLK_DIV2_DIV 141
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#define CLKID_VCLK_DIV2 142
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#define CLKID_VCLK_DIV4_DIV 143
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#define CLKID_VCLK_DIV4 144
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#define CLKID_VCLK_DIV6_DIV 145
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#define CLKID_VCLK_DIV6 146
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#define CLKID_VCLK_DIV12_DIV 147
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#define CLKID_VCLK_DIV12 148
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#define CLKID_VCLK2_IN_EN 150
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#define CLKID_VCLK2_DIV1 151
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#define CLKID_VCLK2_DIV2_DIV 152
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#define CLKID_VCLK2_DIV2 153
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#define CLKID_VCLK2_DIV4_DIV 154
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#define CLKID_VCLK2_DIV4 155
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#define CLKID_VCLK2_DIV6_DIV 156
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#define CLKID_VCLK2_DIV6 157
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#define CLKID_VCLK2_DIV12_DIV 158
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#define CLKID_VCLK2_DIV12 159
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#define CLKID_CTS_ENCT_SEL 160
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#define CLKID_CTS_ENCP_SEL 162
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#define CLKID_CTS_ENCI_SEL 164
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#define CLKID_HDMI_TX_PIXEL_SEL 166
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#define CLKID_CTS_ENCL_SEL 168
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#define CLKID_CTS_VDAC0_SEL 170
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#define CLKID_HDMI_SYS_SEL 172
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#define CLKID_HDMI_SYS_DIV 173
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#define CLKID_MALI_0_SEL 175
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#define CLKID_MALI_0_DIV 176
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#define CLKID_MALI_0 177
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#define CLKID_MALI_1_SEL 178
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#define CLKID_MALI_1_DIV 179
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#define CLKID_MALI_1 180
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#define CLKID_GP_PLL_DCO 181
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#define CLKID_GP_PLL 182
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#define CLKID_VPU_0_SEL 183
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#define CLKID_VPU_0_DIV 184
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#define CLKID_VPU_0 185
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#define CLKID_VPU_1_SEL 186
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#define CLKID_VPU_1_DIV 187
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#define CLKID_VPU_1 189
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#define CLKID_VDEC_1_SEL 191
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#define CLKID_VDEC_1_1_DIV 192
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#define CLKID_VDEC_1_1 193
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#define CLKID_VDEC_1_2_DIV 194
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#define CLKID_VDEC_1_2 195
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#define CLKID_VDEC_HCODEC_SEL 197
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#define CLKID_VDEC_HCODEC_DIV 198
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#define CLKID_VDEC_2_SEL 200
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#define CLKID_VDEC_2_DIV 201
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#define CLKID_VDEC_HEVC_SEL 203
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#define CLKID_VDEC_HEVC_DIV 204
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#define CLKID_VDEC_HEVC_EN 205
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#define CLKID_CTS_AMCLK_SEL 207
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#define CLKID_CTS_AMCLK_DIV 208
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#define CLKID_CTS_MCLK_I958_SEL 210
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#define CLKID_CTS_MCLK_I958_DIV 211
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#define CLKID_VCLK_EN 214
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#define CLKID_VCLK2_EN 215
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#define CLKID_VID_PLL_LVDS_EN 216
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#define CLKID_HDMI_PLL_DCO_IN 217
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/*
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* include the CLKID and RESETID that have
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* been made part of the stable DT binding
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@ -100,29 +100,126 @@
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#define CLKID_MPLL0 93
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#define CLKID_MPLL1 94
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#define CLKID_MPLL2 95
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#define CLKID_MPLL0_DIV 96
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#define CLKID_MPLL1_DIV 97
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#define CLKID_MPLL2_DIV 98
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#define CLKID_CPU_IN_SEL 99
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#define CLKID_CPU_IN_DIV2 100
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#define CLKID_CPU_IN_DIV3 101
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#define CLKID_CPU_SCALE_DIV 102
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#define CLKID_CPU_SCALE_OUT_SEL 103
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#define CLKID_MPLL_PREDIV 104
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#define CLKID_FCLK_DIV2_DIV 105
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#define CLKID_FCLK_DIV3_DIV 106
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#define CLKID_FCLK_DIV4_DIV 107
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#define CLKID_FCLK_DIV5_DIV 108
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#define CLKID_FCLK_DIV7_DIV 109
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#define CLKID_NAND_SEL 110
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#define CLKID_NAND_DIV 111
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#define CLKID_NAND_CLK 112
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#define CLKID_PLL_FIXED_DCO 113
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#define CLKID_HDMI_PLL_DCO 114
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#define CLKID_PLL_SYS_DCO 115
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#define CLKID_CPU_CLK_DIV2 116
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#define CLKID_CPU_CLK_DIV3 117
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#define CLKID_CPU_CLK_DIV4 118
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#define CLKID_CPU_CLK_DIV5 119
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#define CLKID_CPU_CLK_DIV6 120
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#define CLKID_CPU_CLK_DIV7 121
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#define CLKID_CPU_CLK_DIV8 122
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#define CLKID_APB_SEL 123
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#define CLKID_APB 124
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#define CLKID_PERIPH_SEL 125
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#define CLKID_PERIPH 126
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#define CLKID_AXI_SEL 127
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#define CLKID_AXI 128
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#define CLKID_L2_DRAM 130
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#define CLKID_L2_DRAM_SEL 129
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#define CLKID_HDMI_PLL_LVDS_OUT 131
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#define CLKID_HDMI_PLL_HDMI_OUT 132
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#define CLKID_VID_PLL_IN_SEL 133
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#define CLKID_VID_PLL_IN_EN 134
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#define CLKID_VID_PLL_PRE_DIV 135
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#define CLKID_VID_PLL_POST_DIV 136
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#define CLKID_VID_PLL_FINAL_DIV 137
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#define CLKID_VCLK_IN_SEL 138
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#define CLKID_VCLK_IN_EN 139
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#define CLKID_VCLK_DIV1 140
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#define CLKID_VCLK_DIV2_DIV 141
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#define CLKID_VCLK_DIV2 142
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#define CLKID_VCLK_DIV4_DIV 143
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#define CLKID_VCLK_DIV4 144
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#define CLKID_VCLK_DIV6_DIV 145
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#define CLKID_VCLK_DIV6 146
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#define CLKID_VCLK_DIV12_DIV 147
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#define CLKID_VCLK_DIV12 148
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#define CLKID_VCLK2_IN_SEL 149
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#define CLKID_VCLK2_IN_EN 150
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#define CLKID_VCLK2_DIV1 151
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#define CLKID_VCLK2_DIV2_DIV 152
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#define CLKID_VCLK2_DIV2 153
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#define CLKID_VCLK2_DIV4_DIV 154
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#define CLKID_VCLK2_DIV4 155
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#define CLKID_VCLK2_DIV6_DIV 156
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#define CLKID_VCLK2_DIV6 157
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#define CLKID_VCLK2_DIV12_DIV 158
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#define CLKID_VCLK2_DIV12 159
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#define CLKID_CTS_ENCT_SEL 160
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#define CLKID_CTS_ENCT 161
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#define CLKID_CTS_ENCP_SEL 162
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#define CLKID_CTS_ENCP 163
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#define CLKID_CTS_ENCI_SEL 164
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#define CLKID_CTS_ENCI 165
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#define CLKID_HDMI_TX_PIXEL_SEL 166
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#define CLKID_HDMI_TX_PIXEL 167
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#define CLKID_CTS_ENCL_SEL 168
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#define CLKID_CTS_ENCL 169
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#define CLKID_CTS_VDAC0_SEL 170
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#define CLKID_CTS_VDAC0 171
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#define CLKID_HDMI_SYS_SEL 172
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#define CLKID_HDMI_SYS_DIV 173
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#define CLKID_HDMI_SYS 174
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#define CLKID_MALI_0_SEL 175
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#define CLKID_MALI_0_DIV 176
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#define CLKID_MALI_0 177
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#define CLKID_MALI_1_SEL 178
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#define CLKID_MALI_1_DIV 179
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#define CLKID_MALI_1 180
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#define CLKID_GP_PLL_DCO 181
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#define CLKID_GP_PLL 182
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#define CLKID_VPU_0_SEL 183
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#define CLKID_VPU_0_DIV 184
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#define CLKID_VPU_0 185
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#define CLKID_VPU_1_SEL 186
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#define CLKID_VPU_1_DIV 187
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#define CLKID_VPU_1 189
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#define CLKID_VPU 190
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#define CLKID_VDEC_1_SEL 191
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#define CLKID_VDEC_1_1_DIV 192
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#define CLKID_VDEC_1_1 193
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#define CLKID_VDEC_1_2_DIV 194
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#define CLKID_VDEC_1_2 195
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#define CLKID_VDEC_1 196
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#define CLKID_VDEC_HCODEC_SEL 197
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#define CLKID_VDEC_HCODEC_DIV 198
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#define CLKID_VDEC_HCODEC 199
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#define CLKID_VDEC_2_SEL 200
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#define CLKID_VDEC_2_DIV 201
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#define CLKID_VDEC_2 202
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#define CLKID_VDEC_HEVC_SEL 203
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#define CLKID_VDEC_HEVC_DIV 204
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#define CLKID_VDEC_HEVC_EN 205
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#define CLKID_VDEC_HEVC 206
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#define CLKID_CTS_AMCLK_SEL 207
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#define CLKID_CTS_AMCLK_DIV 208
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#define CLKID_CTS_AMCLK 209
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#define CLKID_CTS_MCLK_I958_SEL 210
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#define CLKID_CTS_MCLK_I958_DIV 211
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#define CLKID_CTS_MCLK_I958 212
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#define CLKID_CTS_I958 213
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#define CLKID_VCLK_EN 214
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#define CLKID_VCLK2_EN 215
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#define CLKID_VID_PLL_LVDS_EN 216
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#define CLKID_HDMI_PLL_DCO_IN 217
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#endif /* __MESON8B_CLKC_H */
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