x86/msr: Prepare for including <linux/percpu.h> into <asm/msr.h>
To clean up the per CPU insanity of UP which causes sparse to be rightfully unhappy and prevents the usage of the generic per CPU accessors on cpu_info it is necessary to include <linux/percpu.h> into <asm/msr.h>. Including <linux/percpu.h> into <asm/msr.h> is impossible because it ends up in header dependency hell. The problem is that <asm/processor.h> includes <asm/msr.h>. The inclusion of <linux/percpu.h> results in a compile fail where the compiler cannot longer handle an include in <asm/cpufeature.h> which references boot_cpu_data which is defined in <asm/processor.h>. The only reason why <asm/msr.h> is included in <asm/processor.h> are the set/get_debugctlmsr() inlines. They are defined there because <asm/processor.h> is such a nice dump ground for everything. In fact they belong obviously into <asm/debugreg.h>. Move them to <asm/debugreg.h> and fix up the resulting damage which is just exposing the reliance on random include chains. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20240304005104.454678686@linutronix.de
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@ -17,6 +17,7 @@
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#include <linux/kvm_host.h>
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#include <asm/cpufeature.h>
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#include <asm/debugreg.h>
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#include <asm/hardirq.h>
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#include <asm/intel-family.h>
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#include <asm/intel_pt.h>
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@ -5,6 +5,7 @@
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#include <linux/sched/clock.h>
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#include <asm/cpu_entry_area.h>
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#include <asm/debugreg.h>
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#include <asm/perf_event.h>
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#include <asm/tlbflush.h>
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#include <asm/insn.h>
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@ -5,7 +5,9 @@
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#include <linux/bug.h>
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#include <linux/percpu.h>
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#include <uapi/asm/debugreg.h>
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#include <asm/cpufeature.h>
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#include <asm/msr.h>
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DECLARE_PER_CPU(unsigned long, cpu_dr7);
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@ -159,4 +161,26 @@ static inline unsigned long amd_get_dr_addr_mask(unsigned int dr)
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}
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#endif
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static inline unsigned long get_debugctlmsr(void)
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{
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unsigned long debugctlmsr = 0;
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#ifndef CONFIG_X86_DEBUGCTLMSR
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if (boot_cpu_data.x86 < 6)
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return 0;
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#endif
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rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
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return debugctlmsr;
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}
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static inline void update_debugctlmsr(unsigned long debugctlmsr)
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{
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#ifndef CONFIG_X86_DEBUGCTLMSR
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if (boot_cpu_data.x86 < 6)
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return;
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#endif
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wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
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}
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#endif /* _ASM_X86_DEBUGREG_H */
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@ -6,7 +6,7 @@
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#ifdef CONFIG_X86_64
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#include <asm/msr-index.h>
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#include <asm/msr.h>
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/*
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* Read/write a task's FSBASE or GSBASE. This returns the value that
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@ -576,28 +576,6 @@ extern void cpu_init(void);
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extern void cpu_init_exception_handling(void);
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extern void cr4_init(void);
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static inline unsigned long get_debugctlmsr(void)
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{
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unsigned long debugctlmsr = 0;
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#ifndef CONFIG_X86_DEBUGCTLMSR
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if (boot_cpu_data.x86 < 6)
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return 0;
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#endif
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rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
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return debugctlmsr;
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}
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static inline void update_debugctlmsr(unsigned long debugctlmsr)
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{
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#ifndef CONFIG_X86_DEBUGCTLMSR
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if (boot_cpu_data.x86 < 6)
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return;
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#endif
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wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
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}
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extern void set_task_blockstep(struct task_struct *task, bool on);
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/* Boot loader type from the setup header: */
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@ -2,11 +2,11 @@
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#ifndef _ASM_X86_SPECIAL_INSNS_H
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#define _ASM_X86_SPECIAL_INSNS_H
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#ifdef __KERNEL__
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#include <asm/nops.h>
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#include <asm/processor-flags.h>
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#include <linux/errno.h>
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#include <linux/irqflags.h>
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#include <linux/jump_label.h>
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@ -7,6 +7,8 @@
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* Author:
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* Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
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*/
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#include <linux/bug.h>
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#include <linux/limits.h>
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#include <asm/cpufeature.h>
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#include <asm/intel_pconfig.h>
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@ -6,6 +6,7 @@
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* Authors: Fenghua Yu <fenghua.yu@intel.com>,
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* H. Peter Anvin <hpa@linux.intel.com>
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*/
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#include <linux/printk.h>
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#include <asm/processor.h>
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#include <asm/archrandom.h>
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@ -2,6 +2,8 @@
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/*
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* x86 FPU bug checks:
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*/
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#include <linux/printk.h>
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#include <asm/cpufeature.h>
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#include <asm/fpu/api.h>
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@ -6,7 +6,9 @@
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#include <linux/sched/task_stack.h>
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#include <linux/mm.h>
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#include <linux/ptrace.h>
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#include <asm/desc.h>
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#include <asm/debugreg.h>
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#include <asm/mmu_context.h>
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unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs)
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