dt-bindings: pinctrl: pinctrl-zynq: Convert to yaml
Convert the Zynq pinctrl binding file to yaml. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1626868353-96475-2-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Sai Krishna Potthuri
Linus Walleij
parent
6ceb3c6406
commit
153df45acd
@ -1,105 +0,0 @@
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Binding for Xilinx Zynq Pinctrl
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Required properties:
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- compatible: "xlnx,zynq-pinctrl"
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- syscon: phandle to SLCR
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- reg: Offset and length of pinctrl space in SLCR
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Zynq's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, slew rate, etc.
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Each configuration node can consist of multiple nodes describing the pinmux and
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pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Required properties for pinmux nodes are:
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- groups: A list of pinmux groups.
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- function: The name of a pinmux function to activate for the specified set
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of groups.
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Required properties for configuration nodes:
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One of:
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- pins: a list of pin names
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- groups: A list of pinmux groups.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pinmux subnode:
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groups, function
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pinconf subnode:
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groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
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low-power-disable, low-power-enable
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Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
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respectively.
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Valid values for groups are:
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ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
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qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
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spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
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spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
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sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
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sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
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can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
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uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp,
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ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
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gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
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Valid values for pins are:
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MIO0 - MIO53
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Valid values for function are:
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ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
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spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
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sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
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smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
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i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
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The following driver-specific properties as defined here are valid to specify in
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a pin configuration subnode:
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- io-standard: Configure the pin to use the selected IO standard according to
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this mapping:
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1: LVCMOS18
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2: LVCMOS25
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3: LVCMOS33
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4: HSTL
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Example:
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pinctrl0: pinctrl@700 {
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compatible = "xlnx,pinctrl-zynq";
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reg = <0x700 0x200>;
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syscon = <&slcr>;
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_10_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_10_grp";
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slew-rate = <0>;
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io-standard = <1>;
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};
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conf-rx {
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pins = "MIO49";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO48";
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bias-disable;
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};
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};
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};
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216
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
Normal file
216
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
Normal file
@ -0,0 +1,216 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Zynq Pinctrl
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maintainers:
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- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
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description: |
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Zynq's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, slew rate, etc.
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Each configuration node can consist of multiple nodes describing the pinmux and
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pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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properties:
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compatible:
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const: xlnx,zynq-pinctrl
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reg:
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description: Specifies the base address and size of the SLCR space.
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maxItems: 1
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syscon:
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description:
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phandle to the SLCR.
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patternProperties:
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'^(.*-)?(default|gpio)$':
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type: object
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patternProperties:
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'^mux':
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type: object
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description:
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Pinctrl node's client devices use subnodes for pin muxes,
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which in turn use below standard properties.
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$ref: pinmux-node.yaml#
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properties:
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groups:
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description:
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List of groups to select (either this or "pins" must be
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specified), available groups for this subnode.
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items:
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enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp,
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mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk,
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qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp,
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spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0,
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spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1,
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spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp,
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spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2,
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spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0,
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spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1,
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spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
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sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp,
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sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
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sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp,
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smc0_nor_addr25_grp, smc0_nand, can0_0_grp, can0_1_grp,
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can0_2_grp, can0_3_grp, can0_4_grp, can0_5_grp,
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can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp,
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can0_10_grp, can1_0_grp, can1_1_grp, can1_2_grp,
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can1_3_grp, can1_4_grp, can1_5_grp, can1_6_grp,
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can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp,
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can1_11_grp, uart0_0_grp, uart0_1_grp, uart0_2_grp,
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uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp,
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uart0_7_grp, uart0_8_grp, uart0_9_grp, uart0_10_grp,
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uart1_0_grp, uart1_1_grp, uart1_2_grp, uart1_3_grp,
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uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp,
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uart1_8_grp, uart1_9_grp, uart1_10_grp, uart1_11_grp,
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i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp,
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i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
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i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, i2c1_0_grp,
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i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, i2c1_4_grp,
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i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp,
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i2c1_9_grp, i2c1_10_grp, ttc0_0_grp, ttc0_1_grp,
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ttc0_2_grp, ttc1_0_grp, ttc1_1_grp, ttc1_2_grp,
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swdt0_0_grp, swdt0_1_grp, swdt0_2_grp, swdt0_3_grp,
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swdt0_4_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp,
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gpio0_3_grp, gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
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gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, gpio0_10_grp,
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gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp,
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gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
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gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, gpio0_22_grp,
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gpio0_23_grp, gpio0_24_grp, gpio0_25_grp, gpio0_26_grp,
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gpio0_27_grp, gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
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gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, gpio0_34_grp,
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gpio0_35_grp, gpio0_36_grp, gpio0_37_grp, gpio0_38_grp,
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gpio0_39_grp, gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
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gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, gpio0_46_grp,
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gpio0_47_grp, gpio0_48_grp, gpio0_49_grp, gpio0_50_grp,
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gpio0_51_grp, gpio0_52_grp, gpio0_53_grp, usb0_0_grp,
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usb1_0_grp]
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maxItems: 54
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function:
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description:
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Specify the alternative function to be configured for the
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given pin groups.
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enum: [ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk,
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qspi_cs1, spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc,
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sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
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smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0,
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can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0,
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usb0, usb1]
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required:
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- groups
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- function
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additionalProperties: false
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'^conf':
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type: object
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description:
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Pinctrl node's client devices use subnodes for pin configurations,
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which in turn use the standard properties below.
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$ref: pincfg-node.yaml#
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properties:
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groups:
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description:
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List of pin groups as mentioned above.
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pins:
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description:
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List of pin names to select in this subnode.
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items:
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pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
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maxItems: 54
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bias-pull-up: true
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bias-pull-down: true
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bias-disable: true
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bias-high-impedance: true
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low-power-enable: true
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low-power-disable: true
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slew-rate:
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enum: [0, 1]
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io-standard:
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description:
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Selects the IO standard for MIO pins, this is driver specific.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum: [1, 2, 3, 4]
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oneOf:
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- required: [ groups ]
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- required: [ pins ]
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- syscon
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additionalProperties: false
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examples:
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- |
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pinctrl0: pinctrl@700 {
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compatible = "xlnx,zynq-pinctrl";
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reg = <0x700 0x200>;
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syscon = <&slcr>;
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_10_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_10_grp";
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slew-rate = <0>;
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io-standard = <1>;
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};
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conf-rx {
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pins = "MIO49";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO48";
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bias-disable;
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};
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};
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};
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uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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...
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